TPS3705: Watchdog function

Jeril,

Do you have any scope shots of your example here? WDO should go down.

Thanks,

Abhinav.

How do I add the scope captures here?

is there a way I can attach?

Jeril,

Yes, please save images and you can attach in your reply by using the "Insert/Edit Media" option in the toolbar above the text box.

Thanks,
Abhinav.

Jeril,

It seems like your WDO is latching high for some reason. Do you have a schematic of your application I can see?

Thanks,
Abhinav.

reference schematic.pdf

Jeril,

Are you disconnecting WDI when you are testing or connecting to GND?

Thanks,
Abhinav.

The WDI is pulled to GND while tested

Hello TI team,

Are there any further updates on this case?

Regards
Jeril

Jeril,

I'm working on getting some answers for you from our product experts on this part and we are trying to figure out what went wrong with your application. I will try to report back to you by next week.

Thanks,
Abhinav.

Hi Jeril,

I've been looking into this, I want to verify a few things. Your resistor divider on PFI calculates to 2.506 V but it seems like you are looking for a threshold of 1.25V? Also, is the device in RESET when you are testing the WDO?

Thanks,
Abhinav.

Hi

Do you have an update on this?? Its getting delayed and we expect to close the design this week

Please let me know if this is a limitation of the chip

Hi Jeril,

As in my message above, could you clarify these things?

"I've been looking into this, I want to verify a few things. Your resistor divider on PFI calculates to 2.506 V but it seems like you are looking for a threshold of 1.25V? Also, is the device in RESET when you are testing the WDO?"

Thanks,

Abhinav.

I thought I did respond to this, but i dont see it in this thread.

The resistor divider you mentioned is correct, out design is checking for a threshold of 1.25V below which the PFO signal will be active
The device reset signal is not triggered.

The MR signal is not changing when the WDI is pulled low, if thats your question.

Jeril,

I'm basically trying to figure out whether or not your device is in a "don't care" section for WDI. If your RESET is low during this time, changes on WDI will not affect WDO. I attached the timing diagram for more clarity.

Thanks,

Abhinav.

Jeril,

Do you know if this was the issue? I noticed you have not responded so you may have resolved your issue. I will close the thread for now but let me know if you need more support.

Thanks,

Abhinav.

Abhinav,

thanks for the follow up.The reset gets pulled low. But not sure why. The MR is stable. Only variable is the WDI signal. refer attached scope capture

What is the best way to test the Watchdog functionality

regards

jeril

Hi Jeril,

I'm not sure why the RESET is being pulled low either. The WDO should be pulled low, but I want to ask if you can disconnect anything connected to WDO. I feel like its being pulled up somehow and I'm not sure what it is.

The best way to test WD functionality is to provide a pulse on WDI and then remove it and make it low.

Thanks,

Abhinav.

Hi I thought I had shared you in the past as well. the WDO is not pulled up anywhere. attached is the schematics.

The way we are testing is Pulling WDI for 2secs or more and observing WDO

regards
Jeril

Jeril,

I believe what is happening is that because your device is resetting, this is triggering the "don't care" for the WDI. This causes no output to the WDO. I believe there is an issue on your RESET causing the whole sequence to happen.

Thanks,
Abhinav.

Hi Abhinav,

Can the reset be triggered without any changes in the /MR signal? I see that the /MR signal is consistent.

are there other lines which can influence the reset output of the IC?

Regards

Jeril

Jeril,

The only factors that should bring RESET down will be Vdd falling below 2.63 V or MR being forced low.

Thanks,
Abhinav.

HI Abhinav,

I see this discussion not going anywhere close to a solution. Is there something that you want us to try out again? I have provided the timing diagram in actuals and I am not able to understand why the reset should be pulled low at this stage.

Does this mean that the chips WDO will not function just with the WDI signal? is our system logic wrong?

It would be helpful if TI can assign an onsite engineer to look into it and close this ASAP. We need to freeze the design ASAP

Hope you will understand the urgency.

regards
Jeril

Hi Jeril,

I understand the urgency. I want to assure you we're working on your issue with priority. I want to ask about the inverters you're using (SN74LVC3G14) on your RESET, WDO, and PFO lines. My question is, why are you using these? Are you trying to invert the signal because of the MCU? Also, in these scope shots, are you probing these signals after the inverters?

If you wish to take this offline and over email, you can reach out to me over E2E private messaging and I can set up an email thread.

Thanks,
Abhinav.

Hi Abhinav,

Those invertors are for managing the device logic. There are some gates after that for getting a few logics for the controller error states.

Do you see a concern there?

This is not helping. An email thread would accelerate the closure. Please initiate the same.

Else, you could email me at jeril.jose@ge.com

Thanks

Hi Jeril,

I think we have some suggestions for you, I think its best to disconnect the WDO circuitry from MR and test. I have set up an email thread with you and hopefully we can close offline.

Thanks,
Abhinav.