LM5067: Request a Design review and Check a waveform

Hi Louis,

Can you share filled up design calculator to review the design. It is available at http://www.ti.com/product/LM5067/toolssoftware

Best Regards,

Rakesh

Hi Rakesh

I attach the design calculator file.

1121.LM5067_Design_Calculator_REV_E.xlsx

Best Regards

Hi Louis,

Thanks for the sheet. The FET SOA current data needs to be taken at max input voltage 72V.

The SOA of IRF100B201 FET is weak, please consider PSMN4R8-100BSE

The following videos help you on how to use the Design Calculator. Please go through them and send me revised tool for review. Thanks!

https://training.ti.com/node/1133677

https://training.ti.com/node/1133673

https://training.ti.com/node/1133664

https://training.ti.com/node/1133681

Best Regards, 

Rakesh

Hi Rakesh

Thanks for your support.

Except SOA, are there any problems in the circuit?

Best regards.

Hi Louis,

Use Rs (F40) 2mOhm and set Powerlimit higher than F70 Cell value

Best Regards,

Rakesh

Hi Rakesh

The PSMN4R8-100BSE you recommend is different from the package and can not be used.

 is FDP036N10A avalible to use for better SOA than IRF100B201?

Thanks.

Best regards.

Hi Louis,

Understood. Please use design calculator to verify SOA margin

Best Regards,

Rakesh

Hi Louis,

Please let me know if any help is needed on this design.

Best Regards,

Rakesh

Hi Rakesh

Purple : Vds, Skyblue :Vgs, Green : Ids

Normal waveform

Abnormal Waveform: One FET Damage(Drain -Source Short)

Best Regards.

Hi Louis,

Looks the design does not have enough SOA margin during startup. Is the FET failure repeatable ?

Best Regards,

Rakesh

Hi Rakesh

70 out of a total of 12,000.

If the SOA margin becomes a problem, should not the failure rate be higher?

Thanks.

Best regarads.

Hi Louis,

Not necessarily as there can be mismatch between FET to FET. Is there any difference in startup load conditions for the failed board and passed boards?

Are you able to fill the design calculator to check the SOA margin.?

Who is the customer? Did you have local TI field engineer support to have look?

Best Regards,

Rakesh

Hi Rakesh

Thanks for your fast Feedback.

All Startup load Condition is same.

we changed the FET to FDP036N10A. and Tested it.

SOA of FDP036N10A is better then IRF100B201.

but failer rate is higher then IRF100B201.

Best Regards.

Hi Louis,

Can you increase GATE capacitance on misbehaved board and check the startup profile again.

Also, I am waiting for design calculator. Please send separate sheets for each FET.

Best Regards,

Rakesh

Hi Rakesh

Hi Louis,

Ok.

Use 0.22uF on the misbehaved board and test. 

Best Regards,

Rakesh

Hi Louis,

Did that helped ?

Best Regards,

Rakesh

Hi Louis,

Any update ?

Best Regards,

Rakesh

Hi Rakesh

I will update after test.

Best Regards.

Hi Rakesh

I have attached a startup profile that I changed and tested the gate capacitor.

GATE Capacitor : 0.22uF

Best Regards.

Hi Louis,

The inrush current profile looks good now. Please let me know if you have any other issues

Best Regards,

Rakesh

Hi.

Thanks for the answer.

I have additional questions.

Please tell us why you increased the gate capacitance value.

Does capacity value change help with SOA margins?

Thank you.

Thanks for the answer.

I do not know much.
I have additional questions.

1. Please explain about DVD control mode operation.

2. Is setting the inrush current low enough to get the SOA margin of the current applied IRF100B201?

Decreasing the resistance of the PWR pin lowers the inrush current.

Is it OK to lower the resistance of the PWR pin to get the current IRF100B201 SOA margin?

3. Tested now is the worst condition.

     However, the actual field supply voltage is 48V to 54V.

     Is there any other problem when the maximum voltage of the field is supplied to 54V?

     It is 12V lower than the voltage tested.

     54V => IRF100B201 Is there any SOA margin?

Thank you.

Hi.

I would like to hear your opinion.

The point of the current question is SOA.

He said a lack of margin of SOA in the schematic of our products.

Currently, more than 22,000 products are produced.
(Production of 22,000 units / generation of 100 defective units)

If SOA margin is bad, I think it is difficult to produce so many products in a short time.

I can think of it as a margin shortage,
In my opinion,
It may be caused by the internal wafer (?) Of MOS-FET or other characteristics.

Do you have any other comments?

Thank you.

Hi Kim,

1A) The application report http://www.ti.com/lit/an/slva673a/slva673a.pdf covers the design aspects of hot-swap system. The power limit and dvdt control are covered. Please go through it

2A) 3A) we suggest to use stronger FET having single slope power limit lines. The FET like IRF100B201 has double slope and are prone to thermal instability during startup, current limit mode of operation. The recommended FET is PSMN4R8-100BSE

Best Regards,

Rakesh

Hi Kim,

FET to FET variation in process/parameter, operating temperature and loading differences may be the reason to see failures on some of the boards. I suggest to take few boards and do all the critical tests at max. Vin (54V), max. operating temperature.

Critical tests are

• startup
• startup into short
• short circuit in running condition
• overload

Best Regards,

Rakesh

Thanks for the answer.

The FET you are recommending can not be applied to products that are currently designed.

The product is a different package and can not be replaced.

The current product package is TO-220.

The second question ,

Currently designed products are not protected in case of short circuit during operation.

Q4 or Q5 FET is damaged when short circuit occurs.

How can I protect the FET?

Can I review it if I send you the product?

Thank you.

Thanks for the answer.
The FET you are recommending can not be applied to products that are currently designed.
The product is a different package and can not be replaced.
The current product package is TO-220.

The second question I asked was the FET breakdown question in the short circuit.
Currently designed products are not protected in case of short circuit during operation.
Q4 or Q5 FET is damaged when short circuit occurs.
How can I protect the FET?
And,
Can I review it if I send you the product?
Thank you.

Hi Kim,

You can send me product for verification at our end.

Is short circuit failure repeatable on several boards? 

The GATE capacitance will slow down the turn-off process and puts stress on the FET during short-circuit event. Remove any capacitance on the GATE and do short circuit test again. 

Best Regards,

Rakesh

Hi Kim,

Any update ?

Please let me know what is needed from my side.

Best Regards,

Rakesh

Hi Rakesh