LM5106: LM5106: erratic switching, killing MOSFETs

Hi,

I need to reopen an older case, as we found that the problem that is described there actually still exists.

Your proposed solution is to add a series resistor to the bootstrap capacitor. This seemed to have helped, but in fact it only shifted the necessary conditions. We found that if we allow more time for the bootstrap capacitor to discharge, then the erratic behavior still happens. We also varied the timing. We made sure that IN=1 when EN=0->1, but then the problem occurs later as soon as IN=1->0.

Please see the diagram below (yellow = EN, purple = LS gate, cyan = HS). IN is constant 'high' during this period. I haven't captured the high side gate, but the main supply is ringing heavily (> 10Vpp) from a huge current pulse.

It seems like the LM5106's internal logic has problems with transitioning from unpowered to powered state of the floating high side part. Again, this only shows up when HS > 12V at that moment. But this cannot be avoided in a motor application due to back emf. I am worried that the LM5106 cannot be used at all becuase of this problem?

Kind Regards

Frank

Hello Frank,

Your statement about the main supply having high ripple > 10V peak to peak, is this the main supply to the power MOSFETs or the VDD to the LM5106 IC?

The power main supply to the FETs does not seem like it should have a large transient from charging the boot capacitor, but the VDD of the IC will see the boot cap charging current transient.

Can you confirm if the VDD to the LM5106 is stable, if there is large ripple or droop on VDD that can have the potential to disrupt the operation of the LM5106 due to the possibility of triggering the IC UVLO. Try adding additional capacitance to VDD placed close to the LM5106 pins if there is VDD transients.

Confirm if this addresses your concerns, or you can post additional questions on this thread.

Regards,

Hi Richard,

I made a mistake when explaining the conditions for this problem. I wrote "IN is constant 'high' during this period". Correct is "IN is constant LOW".

Richard Herring said:

Your statement about the main supply having high ripple > 10V peak to peak, is this the main supply to the power MOSFETs or the VDD to the LM5106 IC?

It is the main power MOSFET supply voltage that rings, not the LM5106 VCC. The ringing is because the LM5106 turns on both MOSFETs in the leg at the same time, causing a huge current spike to flow (estimated 3000A).

Richard Herring said:

Can you confirm if the VDD to the LM5106 is stable, if there is large ripple or droop on VDD that can have the potential to disrupt the operation of the LM5106 due to the possibility of triggering the IC UVLO. Try adding additional capacitance to VDD placed close to the LM5106 pins if there is VDD transients.

The voltage drop on VCC from bootstrap charging is approximately 1.5V, and there is no visible ringing. The current circuit already incorporates a 1 ohm  resistor in series with the bootstrap capacitor. I tested increasing that value to 10 and 100 ohms, and I also tested increasing the VCC capacitance from 1uF to 4.7uF - no change for any combination.

I have made new measurements to make the situation more clear. The test condition is the same as before:

- IN is always LOW

- EN is transitioning from LOW to HIGH at the trigger point

- the bootstrap capacitor had time to discharge (2 seconds)

- I am varying the voltage at HS with a bench power supply (47kOhm resistor in series to protect the supply) - this simulates possible back EMF from the motor

- VDD of LM5106 is 10V

Pictures 1 and 2: voltage at HS is < 12V, LM5106 works as normal.

Pictures 3 and 4: voltage at HS is > 12V, LM5106 erratically turns on high side FET.

(Yellow = LO || purple = +48V main supply || cyan = HS || green = HO || white = HO - HS)

PICTURE 1

PICTURE 2 (= zoom of picture 1)

PICTURE 3

PICTURE 4 (= zoom of picture 3)

Regards,

Frank

Hi Richard,

here are more screenshots, this time showing a different set of signals. The test conditions are the same as above. The bootstrap resistor is 22 ohms in this case (bootstrap capacitor is 100nF as always).

(Yellow = LO  ||  purple = VDD  ||  cyan = HB  ||  green = HS  || white = HB-HS)

PICTURE 5: HS voltage < 12V

PICTURE 6: HS voltage > 12V

Regards

Frank

When looking at the signals in picture 6, it seems to me that the LM5106 seems to turn off LO and turn on HO for a period of ~ 1 microsecond, as soon as the bootstrapped supply exceeds UVLO.

As this totally violates the deadtime requirements (LO MOSFET is fully on when this happens), this is definitely erratic behavior of the LM5106 (and also threatening the MOSFETs - 3000A is way beyond its maximum pulse ratings).

We are in a late development phase and close to safety/EMC certification and mass production, therefore I desperately and urgently need to know if there is anything that can be done with or added to the circuit to prevent this from happening.

Regards

Frank

Hi Richard,

Richard Herring said:

pictures 3 and 4 it looks like the LO and HO driver outputs may have pertubations due to the MOSFET miller charge coupled into the gate from the Vds dV/dt

You can see in picture 2 that the gate waveform is absolutely clean. The only difference between pictures 2 and 4 is approximately one volt of difference in initial HS voltage. The phenomenon appears abruptly (almost like digital!): with 11V at HS clean signals, with 12V at HS extreme ringing.

Richard Herring said:

I don't recall what the gate drive resistance between the driver and MOSFET value is.

47 Ohms. We need relatively slow switching speed to keep EMI low. The deadtime setting resistor is 82 kohms.

Richard Herring said:

Confirm that the HB to HS boot capacitance is adequate value to charge the MOSFET Qg

Gate capacitance is 3.6nF, bootstrap capacitor is 100nF hence 27 times bigger.

Richard Herring said:

VDD capacitance is ~10x the HB-HS capacitor value

VDD capacitance is currently ~ 8uF, or ~80x the bootstrap capacitor value. You can see in picture 5 that there is only 520mV of voltage drop from initial bootstrap charging.

The LM5106 layout is very compact, multilayer design and MOSFETs in direct vicinity of the drivers. There is no measurable ringing at all on any of the 10 pins of the LM5106. You can see this clearly from pictures 1,2,5. Please let me repeat, the only difference between all the "clean" and all the "dirty" pictures above is just 1 volt at HS. This is why I am quite confident that this is a problem that lies in the internal circuitry of the LM5106. Just look at pictures 5 and 6 - how do you explain this?

Regards

Frank

Hello Frank,

Since the LM5106 driver is used in a number of motor drive applications and we rarely get feedback of this issue, this may be the 1st, I  am looking at possible causes unique to any given application that can result in this behavior. I see your point that there seems to be some specific condition of triggering the behavior, But it seems if the driver outputs did not respond as expected, not due to some perturbation unique to a given application, we would hear of this type issue quite often.

Can you confirm if the dead time resistor is located very close to the IC and connected with short traces to RDT and VSS, and does not have high dV/dt traces close to the RDT traces. I know you mentioned the layout is very compact.  

It looks like the HO output could be induced by miller charge in pictures 3 & 4, and would still suggest the addition of Vgs capacitance and reducing the gate resistance. You may try adding Vgs capacitance equal to the equivalent gate charge, and reduce the gate resistance by 1/2 to achieve the same switching time.

For picture 6, it is quite possible that once the cross conduction event occurs there is a disturbance to the IC from the high current conduction and associated parasitic trace inductance, that creates an issue with the LO output.

Please confirm if this helps address the concerns.

Regards,

Hi Richard,

Richard Herring said:

this may be the 1st, I  am looking at possible causes unique to any given application that can result in this behavior.

Very understandable!

Richard Herring said:

But it seems if the driver outputs did not respond as expected, not due to some perturbation unique to a given application, we would hear of this type issue quite often.

The duration at which the LM5106 turns on both LS and HS is quite short, around one microsecond. This does not instantly kill the MOSFETs, but leads to a reliability problem as they are repeatedly driven beyond their max ratings. The high current pulse is even audible - it sounds like a faint "click". We have been testing this design for almost one year now and have only found it by chance. I had started investigating after we had shot MOSFETs the first time.

Richard Herring said:

dead time resistor is located very close to the IC and connected with short traces to RDT and VSS, and does not have high dV/dt traces close to the RDT traces

Here is the layout:

Richard Herring said:

It looks like the HO output could be induced by miller charge in pictures 3 & 4

That is definitely not the case. Look at picture 2, you can clearly see that the transition of both gates is butter smooth. There is no sign of miller charge charge induction. All you can see is the short miller plateau of the turn-on process of that MOSFET itself. Scope/probe bandwith is 300MHz, which makes it unlikely that I missed high frequency content.

Richard Herring said:

For picture 6, it is quite possible that once the cross conduction event occurs there is a disturbance to the IC from the high current conduction and associated parasitic trace inductance

The high current conduction is clearly caused by the IC itself. In picture 6, you can see that the entire switching process has already completed (yellow trace has risen to 10V at horizontal DIV 4), before the ringing starts (at DIV 4.5, approximately 1 microsecond later!).

Hello Frank,

The DT resistor does look close, which from your previous description, I expected to be the case. As long as the vias are connected to a low impedance ground plane this should be OK.

Let me research if there is any similar reported behavior and explanation/resolution, although I have been supporting this part for some time.

Regards,

Richard Herring said:

As long as the vias are connected to a low impedance ground plane this should be OK.

Yes, it is a four layer design. Thanks for investigating this!

Cheers, Frank

Hi Richard,

Richard Herring said:

the suggestion I gave regarding the dV/dt induced Vgs was improved

I refer to this as "MOSFET parasitic turn on", which is caused by the upper MOSFET pulling the switch node high very quickly, causing the miller capacitance of the lower MOSFET (forming a capacitive divider with the gate capacitance) to charge that gate up to the point where that transistor turns on. Adding extrnal capacitance to the gate doesn't help in many cases, as the gate's lead inductance adds too much impedance. What I do to mitigate this is either to use negative gate voltage (adding complexity), or choosing MOSFETs with a high Cgs / Cdg ratio. In most cases, this is already enough for a system voltage of up to 50V.

In this case, I am absolutely sure that I do not have parasitic turn on, because a) the MOSFETs are already chosen with this in mind (Ciss = 3600pF, Crss=28pF), and b) switching is relatively slow, ~ 50 ns, and c) there is just no sign of parsitic Vgs rise.

Richard Herring said:

I have devices ordered and coming to our site. I will look to duplicate your conditions in a half bridge power train, concentrating on prebiased HS. to see if I can duplicate this issue.

Much appreciated! I have been working in a technical support department of (former Philips Semiconductors) NXP quite some time ago, and am aware of these "efficiency" policies everywhere. Therefore, it's absolutely awesome to see someone just going after something. We have too many cases where it is just about maximizing profit, and too few where there is actual interest in making better products.

Hello Frank, 

Richard is out of office for business travel this week, he will follow up with you (likely) next week when he gets back with any updates. 

Thanks for your patience.

Regards,

-Mamadou

Hi Mamadou,

thanks for updating me. I hope that Richard can dig into this quickly, as we were in the middle of organizing TÜV safety/EMC certifications of the final product when this happened. We are looking for alternatives in the meantime, but finding a solution with the existing LM5106 would likely save us quite some time and money.

Kind Regards

Frank

Hello Frank,

I have just received the LM5106 devices to test the conditions you refer in your application. I will have to "retrofit" this into a board designed with a different device, so that will take more time than usual to set up the test.

I will start modifying an hopefully be able to test this afternoon.

In the mean time, can you try the suggested addition of gate to source capacitance to see if that improves the situation in your board. I have not seen prior reports of this behavior on the LM5106.

Regards,

Hi Richard,

thanks for following up on this.

Regarding testing additional gate capacitance: I'm sorry but I have to concentrate my efforts on evaluating a backup solution at the moment, for the case that we end up concluding that this problem is unsolvable. That's the one reason why I haven't done this test. The other reason is that I just do not see any causal relation in this case. I've edited one of the earlier pictures here ("picture 6"). The red circle shows the switching action; this takes approximately 50ns. Then there is a 1 microsecond pause during wich the bootstrap capacitor is getting charged. After this one microsecond, the problem happens (yellow circle). At this time, the switching node has long settled. it is much more remarkable that the bootstrap voltage appears to be at the UVLO level. And why does the LS gate voltage drop again? The chip didn't get this command.

Cheers, Frank

Hello Frank,

I have some preliminary test results of the LM5106 driver in a half bridge power train. The component details are VDD capacitance of 1uF and 0.1uf, HB capacitance of 0.1uF, boot diode ES1D-13F, boot resistance 2.2 Ohms, gate resistance 11 Ohms, RDT is 51.1 k Ohms, MOSFETs CSD19531.

I tested the power train with VDD of 10V applied, PWM input signal active initially, and captured the 1^st waveforms after Enable going positive. I had the switch node prebiased at 14V for the following plots, and for these plots had the Vin at ~25V to show the difference of prebias level and high side turn on level.

I am not able to see any disturbance on the low side Vgs or high side Vgs. The waveforms look as expected and very clean.

See below:

Channel 1 is the enable signal, Channel two is the switch node, Channel 3 is the low side Vgs, and channel 1 is the high side Vgs with respect to ground.

Below is the same waveform except that I show the switch node and high side Vgs on the same ground reference. This illustrates better the high side Vgs relative to the switch node, which is the high side ground reference.

I think you were showing the gate drive concern when the switch node was prebiased higher than VDD, which is the case in the plots I recorded.

Now I am not sure what the difference is in the conditions I recorded Vs what you show the issue. I see the gate charge is higher on the On Semi FET’s you have in a schematic you posted on the earlier thread. The NTMFS5C628 is 52nC Vs the CSD19531 at 37nC.

Confirm if the schematic below is the component values you are using.

If you see something that is different in the test sequence or conditions, I can easily test different conditions at this point.

One difference I see is that you have a schottky diode for the boot diode, Vs I have an ultrafast silicon diode. Schottkys are fast recovery of course, but do have higher junction capacitance. I would be surprised if this made a significant difference, but it is a difference I see in the circuits.

Regards,

Hi Richard,

the test circuit has some important changes that also help showing the bug more clearly. Most importantly, the bootstrap charging resistor is 22 ohms, and the gate resistors are 47 ohms. LM5106 VCC is 10V. This is the circuit that the previous oscilloscope pictures belong to:

You also need to zoom into the switching process; the bug is not visible at the timebase that you had made your screenshots with.

It is also very important to let the bootstrap capacitor fully discharge, before enabling the chip. The bug does only appear in this case. My test cycle inhibits the chip for 2 seconds, and then enables/PWM's for a short period, then repeats.

Cheers, Frank

Hello Frank,

I will test again with the value changes you reference for gate resistance, diode resistance, and I see you have 82 kOhms for RDT.

I did zoom in previously on the waveforms and did not see the driver output behavior you show, although I did not post that zoomed in plot. My previous testing was with VDD=10V as you had indicated in your application.

I will retest and confirm the results today.

Regards,

Hi Richard,

thanks, that's confusing on the one hand, but also gives me hope.

Are there different revisions of the LM5106? The chips that I have mounted read "65PE37J 5106SD". Their origin is Digikey.

I will check if there is something happening on PWM and add a 100pF close to the pin. The signal trace is relatively long (~100 mm) and is directly driven by an STM32 GPIO; same for EN. In the meantime, can you please also check PWM? Could the high side driver's exiting UVLO cause a short current spike on that input?

EDIT: I had problems reproducing this myself just now. I then realized that that there is a quite narrow band of the HB bias voltage to reproduce it reliably. And there also seems to be a temperature dependency. For the chip here, it is currently 9.6V to 10.3V (measured with scope, VDD measures 9.7V with the same method). And I am making sure that PWM=0 when EN goes high. That narrow band confuses me here, as I my previous understanding was that there would only be a lower bound, but that is apparently not the case for this particular setup.

And I can also confirm that there is something bad happening with both PWM and EN inputs. The following pictures show PWM (purple, first picture) and EN (purple, second picture) probed at the LM5106 inputs. No capacitance added yet, I will do that now. The third picture shows PWM with HB > 10.3V in contrast, from which you see that the disturbance is not caused by something else in the circuit. It is apparent that the LM5106 does this somehow, likely by sending current pulses out to its inputs. (P.S. I have been using RF probe grounding clips to avoid external RF pickup, I'm pretty sure that this disturbance is real.)

EDIT2:

I've added capacitors at PWM+EN (100pF first, then 1nF in addition). This does not improve the situation.

Cheers, Frank

Richard Herring said:

What I was able to produce, were HO output pulses that were low in amplitude and short duration when VHB-VHS was close to the UVLO rising threshold of ~6V.

The plot below shows VHB level of ~6.16V when LO transitions low. After that point HB to ground voltage floats higher due to SW node prebias. That is followed by the HO going high although short pulse and low amplitude. The HB bias was not high enough to sustain the HO pulse before reaching the HB UVLO falling threshold.

What you observe here is the high side driver attempting to drive its MOSFET, but going back to UVLO because of insufficient bootstrap voltage. This is not what I refer to as my problem, as you do not have a situation where both LO and HO outputs drive their MOSFETs *at the same time*. The chip is still sequencing properly, and I'm perfectly fine with the fact that it might improperly reproduce the first pulse after coming out of shutdown. My problem is that both LO and HO turn on *simultaneously*, and this seems to happen when the high side drivers exits UVLO. You haven't captured that phenonenon yet. You do not need any signal at the PWM input at all, just keep that input LOW. Pulse EN high with a square wave: HIGH = 1millisecond, LOW=2seconds (at least, maybe more). Then vary the HB prebias via your bench supply, and you should be able to see the problem.

Richard Herring said:

In your system, is it necessary to have Enable asserted at any time relative to the PWM input timing?

No, we have full freedom, and I actually had tested biasing PWM static LOW and static HIGH before and after EN going HIGH. With PWM static LOW, I get the problem instantly. With PWM HIGH, I get it as soon as PWM goes LOW for the first time. It only delays the problem occurence.

Richard Herring said:

There is likely some ground bounce

Definitely, as there is 2000 to 3000A of current rushing through the MOSFETs at that moment. Ground potentials are all over the place, and I wouldn't dare to interpret that massive EN/PWM ringing in any way. It is very likely ground bounce, even though I use an RF GND spring clip for that probe. Such a huge amount of EMI can even couple directly into the probe leads (that would be by guess). As mentioned, I can even *hear* that current.

Cheers, Frank

Hi Richard,

thanks for following up on this!

Richard Herring said:

I saw your last response on the email notification I receive, although for some reason I don't see the latest on E2E.

I see everything in my thread history here, can I do something wrong like taggging things private?

Richard Herring said:

I repeated the test with only cycling Enable as you suggested and I am able to capture an HO pulse with an amplitude that is relatively low during the event of Enable going high and LO turning on. What I captured can be explained, and is a result of the miller charge of the high side power MOSFET. This perturbation of the HO pulse exists for a time until the HB capacitor charges to ~2 to 2.5V at which time there is enough voltage for the driver to actively turn on the internal HO pull down device.

Agree, that's clearly gate chargeup through the miller capacitance that you have in your circuit.

Richard Herring said:

The HO output has a diode Vf path to the HB pin and HB capacitance. At 0V bias the HO will be clamped to ~0.6 to 0.7V or maybe higher depending on the current forced into the IC pin. As VDD or VHB-VHS achieves ~2V there is enough voltage to turn on the internal driver pull down device; which is the initialization state when VDD or VHB is below the UVLO threshold, regardless of the driver inputs.

This would mean that "parasitic" voltage at the MOSFET gate cannot be more than ~2.7V, because above that the driver is able to define a clear LOW state while below UVLO. In my case, this is way above Vg,thr (1.2V .. 2.0V) meaning that we could always have situations where one of them could turn on by themselves, while the driver is not powered. That is an existing case in this system - we switch off the gate driver's VCC as part of the eStop solution, while still having the main bus voltage present. This does actually explain our failing MOSFETs best. If, while driver VDD=0, both MOSFETs build up charge at their gates simultaneously for whatever reason (like external EM fields, for example, or moisture), then they will get shot. I got mislead my the LM5106's datasheet here: "When the supply voltage is applied to the VDD pin of the LM5106, the
top and bottom gates are held low until VDD exceeds the UVLO threshold" Because of that I did not add external weak pull down resistors at each gate. There is no hint that this ability gets lost below 2.7V. Many modern MOSFETs have gate threshold voltages below that. Maybe a corresponding note could be added in the datasheet.

Richard Herring said:

Since your power devices have different parameters it is quite possible you are seeing a larger Vgs perturbation due to higher Qdg.

It is the other direction, the used MOSFETs (NTMFS5C628NL) have much less miller capacitance in relation to gate capacitance. A picture that I posted earlier clearly shows that; white is the high side gate voltage. You can barely see it rising when LO turns on:

This is why I am still confident that extra gate capacitance does not help in my case. It would help in yours, but this is only because your MOSFETs have a worse Coss/Ciss ratio. It is also apparent that you haven't seen my particular problem situation yet. I am with you that this is very likely because of the different MOSFETs that you use. That also explains in a way why no other customers have reported this problem yet. It appears to require a very specific component choice, very specific conditions, and also quite some research to actually identify it.

As I mentioned, we had to take quick action, and have meanwhile decided to fully switch to an alternative solution (using UCC20225NPL drivers, also from TI). As these are galvanically isolated, they cannot have any parasitic effects in the high side level shifters, and they also have real gate pull down resistors built in. I am fine if you want to close this thread, but if you wan to continue trying to identify it, then I would be happy to help you in doing this. Please let me know.

Cheers, Frank

We've had such a similar problem for a long time.

When the LM5106 FET driver is disabled for a long period ( > 2 hrs) and enabled afterwards, a shoot through occurs through one of the half bridges.

The workaround for this problem we have, is not to disable the EN-input of the LM5106.

Hi Quang,

thanks for that, at least good to know that I'm not alone with this :-) Keeping EN active is not an option here though, as this is a consumer appliance and we need to disable the motor PWM when it is in idle, in order to avoid audible noise.

Cheers, Frank

Hi Frank,

You are certainly not the only one who encountered this issue, we’ve found this problem already in May 2011 when we first applied this FET driver.

I’m surprised why this issue is not disclosed on the TI’s website.

Good luck with the new device.

Regards,

Quang