TPS3824: WDI pulse and can not RESET

Otsuka-san,

I'm gonna ask for some clarification on your points. At #3, you mention that a 3.3V pulse appears from the output of /RESET. I'm confused what you mean by this. Are you saying that your Vdd is supposed to be 3.3V but it drops to 2.7V and goes to 3.3V momentarily?

Also, do you have scope shots of your "pulse"? I'm confused in general what you mean by the pulse.

To your questions, your WDI needs to be high impedance to prevent a false reset. You also need to provide a rising or falling edge within the watchdog timeout period to ensure that your system does not cause a reset. For question 2, if there is a rising or falling edge provided on WDI and td has expired, RESET should go high assuming your Vdd is still stable above Vth.

Thanks,
Abhinav.

Hi,Abhinav

I'm sorry to confuse you.

Below is a scope shot of the operation.

Regards,

Otsuka

Otsuka-san,

Sorry for the delay, but yes, to reiterate, WDI is high impedance or should be in your design. In addition, your RESET should have came back up after the time delay which i'm not sure is out of the scope shot. Do you have a schematic if this did not happen? It could be a latching issue in your application.

Thanks,

Abhinav.

Hi,Abhinav

The following is a part of the circuit.

The RESET signal is Low in the previous scope shot, but some other devices remain Hi.
Some go back to Hi after about 200 ms once they go Low.
However, those that do not return in about 200 ms after becoming Low remain Low thereafter.
If there is movement even if WDI goes Low, will RESET go Hi?
If so, what can be considered as the cause of the latch?

Regards,

Otsuka

Hi,Abhinav

It is a circuit that has disappeared.

Regards,

Otsuka

Otsuka-san,

I will be testing this in the lab by next week to hopefully get you an answer and close this out.

Thanks,

Abhinav.