Hi Team,
I found that the function block is different between datasheet and EVM user's guide as picture below.
1. So which one is correct?
2. The truth table in datasheet is correct or not?
Thank you very much,
C.T.
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Hi Team,
I found that the function block is different between datasheet and EVM user's guide as picture below.
1. So which one is correct?
2. The truth table in datasheet is correct or not?
Thank you very much,
C.T.
Hi CT,
thanks for reaching out on e2e,
Sorry for the confusion, I will update the datasheet with the correct image. The NAND gate is the correct figure. The logic table reflects IN+ is high (to make the output high) and IN- is low (to enable the device) and then the NAND gate go active low which will turn on OUTH (since it is PMOS) and open OUTL.
let me know if this makes sense or you find any more discrepancies.
Thanks again!