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TPS59641: Question for TPS59641 VCC in INTEL VRD12-IMVP7 test

Part Number: TPS59641

Hi all,

We test intel document 568685-bytrlmd-vr12-imvp7-val-guide-rev0p75.

In the transient from 0A to 8A,PS state from PS2 to PS0 condition,

we found voltage droop PS0 to PS2 is 30.4mV/voltage droop PS2 to PS0 is 42.2mV.

It is over intel spec. 11.25mV.

Please help to apply the suggestion of improving the voltage droop.

Attached file is our schematic and intel test page.tps59641.pdftps59641.pdf

  • Hi Kevin,

    Several possibilities may cause this...

    From schematic perspective

    1. Please check if remote sense connect to the load by 0hom resistor only.

    2. Please check if USR is triggered or not, if not, please change USR setting to the lowest threshold.

    3. Please check if DCR sense matches L/DCR < RC.

    4. Please check if OCP point, if OCL limit controller to provide energy to save undershoot while transient, if yes, please set higher OCP point.

    5. Please check if phase margin is enough or not, then fine tune compensator.

    6. Please check if inductance can be lower(360nH) or not, 560nH might be too large in this application.

    From layout perspective

    1. Please check if layout copper is enough from inductor to output load

    2. Please check if all the MLCC value/qty. are placed by intel's recommendation

    Thanks

    Chasel