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BQ76PL455A-Q1: bq76pl455A-Q1 support bi-direction communication? and how to check BIST

John Chou62
Intellectual 2070 points
Part Number: BQ76PL455A-Q1
Other Parts Discussed in Thread: BQ79606A-Q1

hi Team,

please help on checking the following question

  1. 455 supports bi-direction communication or not? (ring connection)
  2. How to check BIST result?
  3. How Fault_N pin work when error is triggered and non-triggered?  Could you send me the waveform?

Thanks for the help

  • 0
    TI__Mastermind 19795 points

    Hi John,

    Thanks for your question!

    1. Unfortunately the BQ76PL455A-Q1 does not support bi-direction communication (ring connection). If you would like a device with this capability, we have recently released the BQ79606A-Q1 that would be able to do this!

    2. The results of each BIST is dependent upon the specific test being conducted. For more information on each of the tests, please see section 7.6.3.15 of the datasheet for the TSTCONFIG register, where each test is described. For instance, by setting the [VDIG_TEST] bit in TSTCONFIG, the will go into SHUTDOWN if the VDIG drops below its SHUTDOWN threshold, which is what should happen for that test.

    3. The nFAULT pin will be LOW during an unmasked fault condition, and HIGH when there are no faults (in the faults that are unmasked). This is an active low pin. I have provided an image below that shows an example of an nFAULT pin pulling low during a fault.

    Let me know if this answers your questions!

    Regards,

    Vince

    [If I was able to assist you with your issue, please press This resolved my issue. Thanks!]

  • 0 in reply to Vince
    TI__Intellectual 2070 points

    hi Vince, 

    Thanks very much for the quick clarification.

    about no.3, i can not see the image, can you help re-attach it?

    appreciate the help

  • 0 in reply to John Chou62
    TI__Intellectual 2070 points

    3. The nFAULT pin will be LOW during an unmasked fault condition, and HIGH when there are no faults (in the faults that are unmasked). This is an active low pin. Checking on a pic to show example of an nFAULT pin pulling low during a fault.

    So, normal  case Fault_N is kept high and is changed to low when fault is triggered, right?  Fault heart is only for Fault+/- pins?

     

    Do you know why VM pin is -5V?  And how the AFE window comparators use the -5V?

     

    Max error of accuracy for digital die is 54℃. Do you think that 455A uses this kind of thermistor to do thermal shutdown?

     

    If you have 3 stacks of 455A, how MCU communicates with them? How MCU knows the received data is sent by which 455A?

     

    How uniquely and group address work?

    thanks very much for the help

  • 0 in reply to John Chou62
    TI__Mastermind 19795 points

    Hi John,

    -I apologize for the missing image, let me know if the image below is missing again, as it might be an issue with the uploading of this format!

    -The VM pin is -5V to supply a negative bias voltage to the internal circuitry.

    -The temperature values mentioned (54 C) provided for thermal shutdown are only specified by design, and not tested in production (please see footnote 2 in section 6.15 of the datasheet).

    -When 3 devices are stacked, the microcontroller only communicates to the base device. The BQ76PL455A-Q1 devices then propagate the signal to the rest of the devices in the stack. Each device is assigned its own address during the beginning of communications to the device. Please see section 7.3.10 of the datasheet for a full description of the daisy-chain protocol.

    -[EDITED] Section 8.1.4.3 describes device-addressing for a daisy-chain (called auto-addressing). This assigns unique identifiers to each device in the stack.

    Let me know if this answers your questions!

    Regards,

    Vince Toledo

    [If I was able to assist you with your issue, please press This resolved my issue. Thanks!]