When power off to TPS23754, TPS23754 will output two voltage ripple, how to avoid it? below is my customer's schematic and output gif.
This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
When power off to TPS23754, TPS23754 will output two voltage ripple, how to avoid it? below is my customer's schematic and output gif.
Leo,
I believe that we've seen this issue before. Let me confirm with my systems engineer and get back to you.
-Artem
Leo,
After some internal discussion, we believe that you may be hitting the Vc UVLO. Could you please capture a waveform with Vc and VDD1? This would really help us understand the behavior.
In addition can you provide a schematic that includes the output and also clarify P12V and L4_1. I assume that the P12V is the main output and L4_1 is one of the nodes of the output inductor.
-Artem
Hi Leo,
Can you forward the PDF of the schematic? Because I am unable to look at the exact component part numbers/values. Also did you switch any FET components with any alternative part numbers? Please let us know.
Thanks!
Leo, It has been quite some time since there was activity on this thread.
Do you still require our help?
Thanks,
Leo, I am going to close this thread given the lack of a response since end of July.
Should this still require assistance, all you have to do is reply and the thread will automatically "reopen."
Thank you for your local support, and promotion, of PoE products from TI,