TPS65381-Q1: PIN21 shorted to ground

Under normal working conditions：

Input waveform

Output waveform

Measure the output voltage position with a wire. The 3.3v waveform was captured。

Measure the output voltage position with a wire. The 3.3v waveform was captured。

user 6062940:

  I do not understand your question.

First, What is Input voltage waveform? What are you measuring? Where are you measuring? 

What is your output voltage test point? What are you measuring? Where are you measuring?

When you say voltage position with a wire, what is a wire?

Please be specific as to your setup.

Be specific about your test points.

Please ask your question in detail so that I know what you are looking for.

Note:

VDD3/5 (Pin 21) needs a 4.7uf capacitor on the output of the regulator

VDD5 (Pin 20) needs a 4.7uf capacitor on the output of the regulator

VDDIO (pin 22) needs a 100nf capacitor close the pin

 Input voltage： VBAT and GND.  —— Both ends of capacitor C55

Output voltage: 3.3V and GND. —— TPS65381  Pin21 and GND 

Since it is not easy to measure on the circuit board, connect the 3.3v test point to the oscilloscope with a wire lead for measurement.

Hello,

Gordon is currently out for a few days, but I wanted to follow up with a few requests:

1) Can you confirm the values of the decoupling capacitors on pin 21 (output) and pin 27 (input)?

If they are reduced or not present it could explain the noise.

If they are present, please consider probing directly across the capacitor like the measurements for VBAT.

2) With the lead wire being used for the test point, please consider minimizing the loop area created by wire to the probe and the ground clip to the GND connection to reduce coupled switching noise.

Thanks and Best Regards,

Rick S.

Hello,

While Gordon is on vacation, can you please explain your schematic to make sure you don't have two supplies tied together as it appears in the schematic capture.  It looks like you have Pin 22, VDDIO tied to pin 21, VDD3/5 which is normal.  VDD3/5 is normally used as the IO rail in a system and thus is common to be the IO supply (VDDIO) to the TPS65381A-Q1.  However, on the attached image it is impossible to determine if that is tied into a net called 3.3V VCC which is tied to pin 20, VDD5 or it is actually two separate nets and the net symbols are just overlapping making it look like the nets are tied together. Pin 20 is VDD5 is a 5V LDO output and cannot be tied to VDD3/5.

Can you please use all the channels on your scope and provide the a waveform with these signals present, triggered on the rising edge of IGN pin:   IGN, VBATP, VDD6, VDD3/5.     And a second plot with IGN, VCP, VBATP, NRES.