TPS53622: Sense Circuit Design BVSN,BVSP pin

Hi Vikas,

1) VR_HOT# ,SCLK, SDIO,V3p3  etc signals have resistors connected to them without open drain need, please help me why it is and what basis values is chosen.

VR_HOT# is open-drain output, the open drain pull down resistance can be found in the datasheet, in general, resistor between 1k~10k is ok.

SLCK, SDIO pull up resistor is fixed, you need to follow intel's suggestion first and fine tune it if needed later, please check intel PDG for detail.

2) BVSN, BVSP and AVSN , AVSP i understand these are sense pins, is there any intermediatery circuit using betweeen them to output inductor, please suggest.

Connect AVSP/AVSN and BVSP/BVSN to CPU remote sense point directly.

3)Using dual output rail , i understand we need output capacitors for both the rails, but in datasheet it shows only VCCIO needs and VMCP rail only need at inductor side page 114, why is this?

That is follow intel's recommendation, you can change it as long as you think the design can meet transient spec.

4) what is the valley current limit?

Let me give you a hint. This is the explanation from TI blog and you can just type "TI valley current limit" by search engine (google), then it will pop up on the first page.

https://e2e.ti.com/blogs_/b/powerhouse/archive/2018/06/08/understanding-valley-current-limit

Thanks, Chasel.

Hi Vikas,

Please see my comments.

1) VOUT_DROOP , how to specific decide on this parameter ? How this is depends on Load Line. What parameters we consider in choosing Load Line and VDROOP.

VOUT_DROOP = DC LOAD LINE, you need to know the requirement from CPU/ASIC.

2) Is there any recommendation for Loop Compensation? I see page 116 have some reference but no specific calculations is present. Is there any external circuitary recommended for Loop compensation or with programmable PMBus we need to set them.

All the compensation settings is from NVM configuration, there is no external compensator. As for default configuration, for CPU, you can set

• AC_GAIN = 1x
• AC_LL ~= DC LOADLINE
• INT_TIME = 2us
• INT_GAIN = 1x
  

3) I not find any overshoot and undershoot recommendations, please suggest?

For CPU, USR1=180mV, USR2=220mV

4)Is loop compensation required for each rail?

Yes

what are the things needs to consider for the same.

It depends on the ripple/transient can be met in your design or not.

Thanks,

Chasel

Hi Vikas,

www.ti.com/.../slva882

USR1 means four phases will be turned on at the same time while the threshold is triggered.

USR2 means all phases will be turned on at the same time while the threshold is triggered.

Usually for CPU application, USR1/2 will be set at certain range in order to have better undershoot performance.

Thanks

Chasel