This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

BQ78PL116: Reset event 0x0011

Part Number: BQ78PL116

During EMC testing (Immunity test) we experienced multiple device switch-off due to power loss. Power returns back in some seconds. Only reset events with value 0x0011 have been logged. If we manually reset the BMS chip, reset event with value 0x0041 is logged and current time is set to 0. What is the reason for reset 0x0011 and how it is triggered? 

Alex

  • A reset indicated in the safety history can be due to multiple reasons, when a manual reset is issued the command 0x41 will be logged. However in your case, your EMC testing caused OCD2 and OTD conditions. The device then reset. The log recorded those conditions.

  • Am I right that the event logged at reset time is just a copy of the Safety Alert (of Safety Status?) register?

    How can I decode it? 

    Your description corresponds to it, if I assume bit 15 is bit 0... Please explain.

    Alex 

  • That is correct. I think I'm right about the bit order, but please attempt and OTD test and double check as I don't have a board here that I can test with.

  • with simulated OTD there are no reset events:

    discharge FET switches off after some seconds (set to 4), 

    discharge FET switches back on when OTD is removed,

    everything is logged as expected. 

    If we assume that bit order is correct in the DS, 0x0011 will mean HOCD and HWDG.

    Host watchdog is disabled in our configuration. Could it be that HWDG bit is set during some internal events, like brown-out?

    Alex

  • Hi Alex,

    Thanks for replying back with your results. I learned something today, thanks to you. Yeah, a brownout can definitely cause a WD reset. It's very likely to happen in EMC testing.