HI.
I would like to confirm the current limit of TPS561201.
Is "If the monitored current is above the OCL level, the converter maintains low-side FET on and delays the creation of a new set pulse, even the voltage feedback loop requires one, until the current level becomes OCL level or lower." in the data sheet in other words "It operates when the switch current detected by the drain-source voltage of the low side FET exceeds OCL at the next pulse generation timing. In other words, it operates when the "valley" of the switching current is higher than OCL”?
Best regards.
