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LMZM33606: Negative output with External Sync Clock

PingL
Prodigy 170 points
Part Number: LMZM33606

Hello,

I would like to design +15V input to -15.5V 2.5A output with External Sync Clk in 1MHz 5V input on LMZM33606.

Quote with datasheet: External Sync Clock signal requirement: Low <=0.4V, High >= 2V and should not higher than 5.5V reference to AGND

When design with Negative output (IBB), I would like to confirm the Sync Clk require to shifting the clock signal level from <0.4V ~ >2V at first main powerup stage down to < -15.1V ~ > -13.5V (not higher than -10V) at the target -15.5V output. Please correct me if wrong.

If that is the case, I would like to have below circuitry reference with Enable control circuitry from App Note SNVA835B by adding Zener diode to limit the clock amplitude follow the negative output level. Sorry that I haven't EVB in a short time to try some experience on it, need some valuable input on it.

Sync/Mode pull low (Rrt) with 38.3K is set for initial switching frequency at 1MHz.

If there any better solution and recommendation are welcome.

App Note SNVA835B is very helpful, recommend adding with External Clock application circuitry recommendation.

Thanks in advance for support on this case.

Best regards,

Ping

  • 0
    TI__Guru 50120 points

    Hi Ping,

    Thank you for providing this recommendation. The level shifting circuit you have looks correct for external clock application.

    The values you have for the LOW and HIGH look correct:

    • LOW = 0.4 + VOUT = 0.4 - 15.5 = -15.1V
    • HIGH = 2 + VOUT = 2 - 15.5 = -13.5V
    • HIGH_MAX = 5.5 + VOUT = 5.5 - 15.5 = -10V

    The 5V Schottky diode should help provide voltage clamping features.

    Regards,

    Jimmy