I am concerned about the possibility of an undefined state when both inputs are low for a long time. Under this condition, I wonder if FET or circuit leakage could pull the top gate positive slightly. If so, then the gate could eventually charge up enough to enhance the MOSFET slightly, which would then start pulling up the midpoint of the totem pole and HS. Once HS goes above VDD, there is no bias for the top driver and thus no way for it to hold the MOSFET off.
Some gate drivers come with a recommendation to include a high value gate-source resistor to address conditions like this. I don't see any reference to this in the data sheet.
Do I need to include a gate-source pull-down to protect against this condition ?