This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

BQ76200: BQ76200's DSG (NMOS turn on) timing issue

Part Number: BQ76200

Dears,

My customer met a issue when they measure the turn ON timing of NMOS(DSG pin of BQ76200). They compared their measured waveform and out spec and found big difference(140us vs 7us). As below left BQ76200 spec, the ton time is about 7us. While as below right waveform, customer measured about 160us. Customer did try to modify external capactior/resistor value, but no any effect... Could you please help check this? Below attached circuit as well.

      

                                                                                                                                     ( NMOS VGS= DSG output)

  • Hi Garrick,

    The data sheet parameters for rise and fall time specify a load capacitance of 10 nF.  The load of a FET will be dynamic and the example waveform from the application note was likely taken with a FET having a Ciss value < 10 nF.  The schematic shows 4 parallel FETs each with a Ciss of 13 nF typical, so switching will be slower.  Increasing the charge pump capacitor will provide more charge capacity for turning on the FET, but the internal resistance of the driver is fixed.  It looks like they have already minimized the external resistance, it may not be possible for DSG to switch the FET array quickly.