Hello,
The PMIC's VDD1 +1.0V regulator that supplies CVDD1 rail of 66AKG12 processor produces a voltage ripple of about 50mV on our prototype. This is clearly the pulse skipping (PFM mode) power saving feature of the PMIC.
The PMIC datasheet says in chapter 7.2.2.3.2:
" At light load currents, the converter operates in PFM mode and the output voltage ripple is dependent on the output capacitor value and the PFM peak inductor current."
What is the level of "light load"? - this parameter is not defined in the datasheet.
In other words - what is the output current that causes transition from PFM to PWM mode?
We have followed the datasheet recommendation on the size of the output capacitor - 10uF.
The datasheet says:
"Higher output-capacitor values minimize the voltage ripple in PFM mode."
Does the capacitor value reduce the voltage ripple only or does it also reduce the output current threshold for PFM->PWM transition?
Thanks and Regards,
Josef Rypar