This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS7A16A-Q1: EN slew rate question

Part Number: TPS7A16A-Q1
Other Parts Discussed in Thread: TPS7A16-Q1, TPS7A16

In another post, it was stated:

"While rare, TPS7A16-Q1 can experience issues in applications where the EN slew rate is faster than 1.5 V/us (note that our maximum recommended slew rate for EN is 1.5 V/us).  The TPS7A16A-Q1 is less susceptible to the Ven slew rate; however, we still recommend EN slew rates of less than 1.5 V/us."

My questions are:

1. What specific issues or failure occurs with TPS7A16-Q1 when EN slew rate is faster than 1.5 V/ns?  (Latch up, permanent device damage, other)

2. How was the TPS7A16A-Q1 designed to have less susceptibility to fast EN slew rate?

Thanks,

Alan

  • Hi Alan,

    1. What specific issues or failure occurs with TPS7A16-Q1 when EN slew rate is faster than 1.5 V/ns?  (Latch up, permanent device damage, other)

    --A fast-rising/falling enable signal may put the device into an undesired test mode, and during test mode, the output of the LDO becomes high-impedance.

    2. How was the TPS7A16A-Q1 designed to have less susceptibility to fast EN slew rate?

    --TPS7A16A-Q1 implement fixes on this issue over TPS7A16, but the fixes did not completely eliminate the test mode entering with fast slew rate on enable pin. I would suggest to slow down the enable signal by using a capacitor and resistor in series to meet the slew rate requirement.

    Regards,
    Jason Song