Other Parts Discussed in Thread: UCC27714
The case of the UCC27712 is a SOIC-8 with a 1.27mm grid dimension and a spacing
between the pads of 0.67mm maximimum.
So pin 6 ( HS) which is the drain of the lower mosfet is only 0,67mm away from pin 5,
which is the the gate of the lower mosfet, which is 16V away from source potential.
EN 61010 recommends 1.5 mm A&C for circuits supplied from 320V mains and CATII
Commonly used Mosfets as DPak recommend a PCB layout spacing of greater than 1.5mm between Source / Gate
and Drain connections for safety reasons.
In dirty environment or humidity the dimensions of the driver package could be critical.
A coating could be mandatory, finally driving the costs.
What are the basic ideas and proposals from TI?
Regards
Holger Tuerk