Hi,
I am troubled that two-input dual isolated drivers in half-bridge/ full-bridge application.
Please tell me how to improve the output skew.
Also, please tell me how to implement delay matching methods.
Best Regards,
Jim
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Hi,
I am troubled that two-input dual isolated drivers in half-bridge/ full-bridge application.
Please tell me how to improve the output skew.
Also, please tell me how to implement delay matching methods.
Best Regards,
Jim
Hello Jim,
Can you please share schematic of your design for review?
Also what is the part number of the isolated gate driver in your system as well as details of your troubles or problems you are experiencing?
Thank you.
Regards,
-Mamadou
Hi Jim,
Thank you for your question. I work on the applications team in the high power drivers group.
Our dual channel isolated gate drivers have excellent delay matching. For example, UCC21540 has a maximum of 5ns delay matching between OUTA and OUTB. This is generally sufficient for most power systems that use a half-bridge or full-bridge topology.
Are you asking how to use the deadtime (DT pin 6) of our dual channel isolated gate drivers? Please feel free to give me more information, and I’ll try to help you the best that I can.
If this answered your question, could you please press the green button? If not, feel free to ask more questions.
Thanks and best regards,
John
I focus on the output skew.
I want the delay between Output A and Output B can be decrease.
Have any methods can improve?(not use the deadtime)
Hi Jim,
The delay difference between Output A and Output B is already very small, and mainly happens due to die temperature differences between each output die. The best way to decrease delay difference between OUTA and OUTB is to ensure the power dissipation remains roughly equal between each output, so as to equalize the junction temperature of each die.
If you have any scope shots or depictions of your issue, please feel free to share them.
If this answered your question, could you please press the green button?
Thanks,
John