Hi,
Could you please tell me the operation principle for the overcurrent limit including gate control of the internal NMOS FET ?
It would be very helpful if you would share the application note with me.
Best regards,
Kato
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Hi,
Could you please tell me the operation principle for the overcurrent limit including gate control of the internal NMOS FET ?
It would be very helpful if you would share the application note with me.
Best regards,
Kato
Hello Kato-San,
TPS1663 device limits the current in case of overload or over current. It regulates the gate voltage of internal mosfet to limit the current to IOL value (Set by RLIM resistor). If the current exceeds I(FASTRIP) or I(SCP), the internal MOSFET is turned off to prevent excessive flow of current.
This is described in Section 9.3.4 on Page 18 of the datasheet of TPS1663
Hi Lokesh-san,
Thank you for the information.
I would like to confirm just in case, so is my understanding correct that the Rds_on of the internal FET is controlled to limit the current flowing like the linear regulator when the overcurrent flows to the load ?
Best regards,
Kato
Hello Kato-San,
Yes the Rds_on of internal FET is controlled and drop across IN to OUT increases. This increased drop causes power dissipation and increase in temperature of the device. After the junction temperature crosses TSD (Thermal shutdown limit), device is turned OFF.
Hi Lokesh-san,
Thank you for the information.
I would like to confirm again, does TPS1663 control Rds_on by switching the internal FET to "on" or "off" within tCL_PLIM(dly) when the overcurrent flows to the load ? Or is Rds_on controlled linearly by the gate bias voltage ?
So, which is correct ?
Best regards,
Kato
Hello Kato-San,
The gate voltage of internal FET is controlled linearly to limit the output current.