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TPS7A84: LDO fails to power on during a power cycle.

Part Number: TPS7A84

This is not my expertise so please bear with me...  I am operating at 3.3V output with a 3.5V input.  I probe the IN and OUT pins during a power cycle (ON...OFF...ON...OFF).  During the first OFF, the OUT pins maintain ~500mV for 10 seconds before decaying to zero.  If I power ON during that 10 second window, the LDO drops to 0 V instead of supplying 3.3V.  I am following the circuit topology in the datasheet for ANY-OUT operation at 3.3V (Fig. 43).  Just trying to understand what would pull the output down when I am seeing +3.5 at the input and why this is triggered while the output is maintaining at 500mV.  

The power supply is steadily decaying when switched off and the LDO maintains at 500mV until the supply line decays past about 280mV. 

I could put in a bleed resistor to speed the capacitor discharge but want to better understand what is happening here.

Thank you!

  • Hi Jeremy,

    TPS7A84 has an active discharging circuit. This circuit will discharge the output voltage whenever Vin drops below UVLO, or a device is disabled by enable pin. There might be something that prevents the output discharging from 500mV during the two cases that will activate the active discharging circuit.

    Will you share us with your complete schematic and the waveforms of your power cycle tests with at least Vin, Vout, and Enable voltage? Without them, it's very difficult for us to give recommendations.

    Regards,
    Jason

     

     

     

     

     

  • Hi Jeremy,

    Since it has been a week without a reply, we assume that this issue has been resolved.  If this is not the case, please feel free to reply.

    Regards,
    Jason Song

  • Hi Jason,

    Thank you for your help.  I have been called away from the office and will return next week.  Would it be ok to keep this open for another week to give me a chance to respond with more information once I return?

    Thank you,

    Jeremy

  • Hi Jeremy,

    No worries, feel free to post again when you are back.

    Regards,
    Jason Song

  • Adding a file to show two power downs.  One has a long hang-time at about 530mV.  i find that when I turn the instrument back on while the LDO is in this state, Vout can drop to 0V instead of +3.3V.  Not always but can happen.  

    Sometimes it is a much shorter hang time, which is also pictured (I was able to stumble on both of these relatively quickly which isn't always the case.

    I suspect it has something to do with the supplies that output Vin but I want to see if I can verify this latching behavior with you.  Thank you!

    Power-cycling the TPS7A84.pptx

  • Hi Jeremy, 

    I am sorry for the late response. I am currently looking into your issue, and I will get back to you by 9/11/2019. 

    Regards, 
    Jason Song

  • Hi Jeremy, 

    I have reviewed the slides you uploaded. When Vin drops below the UVLO, the active discharge circuit will be activated to fast discharge the output. When Vin drops below UVLO, there is not enough voltage for the device to maintain the active discharge logic. I can also see your output is higher than your input during the powering down and a reverse current event happened. The last slides show that the device is probably damaged as Vin is following your Vout. 

     In area 1, it's the active discharging circuit quickly discharge the output voltage until Vin drops below UVLO and there is not enough voltage to maintain the logics for discharging. In area 2, Vin drops more while Vout maintains at 500mV due to no external load to discharge the output and the reverse current from the output to the input kicked in. 

    Does it make sense?

    Regards, 
    Jason Song

  • Hi Jeremy, 

    I am ordering the EVMs for TPS7A84, and it will arrive mid next week. I plan to check this on a bench to see if I can duplicate the 0.5V output voltage stuck with my setup. 

    Regards, 
    Jason Song

  • Thank you!  I will go through my schematic to identify external loads when switched off.  The circuit is for driving diodes and and active components mainly and I may need to add some discharge circuitry when powered down.  A bleed resistor would be simplest but a bit wasteful.  I'll see what I can do!

  • Yes, if you could have at least some load during power down, the situation will be much improved. 

  • Hi Jeremy, 

    I was able to verify the power-down cycle for TPS7A84, and here is the finding that will hopefully help with your application. 

    1. During power-down, the active discharge circuit will be activated roughly at when Vin drops below 1V. The 1st scope-shots shows the case for Vin dropping to just below 1V and this keeps the active discharging on. The 2nd plot shows when Vin quickly drops below 0.6V, the active discharging circuit is OFF and the output takes a much longer time to be slowly discharged. 

    Gree is Vin and Yellow is Vout. 

    2. The active discharge needs certain voltage to be stay activated, and when Vin drops below 600mV, the active discharging may stop working. 

    3. Once active discharging circuit stops working, if you have big capacitors and have no load to discharge them, your output is likely to stay at where it is. 

    4. Once Vin drops below Vout and creating a voltage difference higher than 0.3V, the ESD protection kicks in and it will then discharge the output. 

    Hope this will help with your application. 

    Regards, 
    Jason Song