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UCC21540: UCC21540: speed limit?

Brian Machesney1
Prodigy 80 points
Part Number: UCC21540

What limits the UCC21540 to 5MHz? The 28ns prop delay with 10ns minimum pulse width seems like they should allow operation beyond 35MHz.

  • 0
    TI__Expert 3355 points

    Hi Brian,

    Thank you for your question. I work on the applications team in the high power drivers group.

    If you look at section 7.5, the 5-MHz limit assumes that a load of 1nF is placed on the output. The part is limited to 5Mhz since power dissipation is directly proportional to the output switching frequency, when driving a capacitive load. If the capacitive load were smaller, you could switch faster.

    The part can switch faster if the system is designed to allow it, without violating the Tj/power dissipation ratings. You can learn more about how to estimate gate driver power loss in section 10.2.2.5 of the datasheet.

    If you have a challenge where you need to switch at much higher frequencies, could you please share more about your project? We have a wide variety of GaN drivers, such as LMG1210, which might fit your requirements.

    If this answered your question, could you please press the green button? If not, feel free to ask more questions.

    Thanks and best regards,

    John

  • 0 in reply to John Geiger
    Prodigy 80 points

    Referring to the values in the table in section 7.5, please check my calculations.

    Conditions: VDDA/B= 12 V, fsw= 5.1 MHz, 1.0-nF load

    Qg = Cg * Vg = 1nF * 12V = 12nC

    Pgsw = 2 * VDDA/B * Qg * fsw = 2 * 12V * 12nC * 5.1MHz = 1.47W (eq 12 in 10.2.2.5)

    This does not agree with the 1.76W value in the table (2 * 880mW). Please help me understand my error.

    Also, is there any power dissipation impact if I operate both gate drivers in-phase, i.e., zero dead time?

  • 0 in reply to Brian Machesney1
    TI__Expert 3355 points

    Hi Brian,

    Your calculation for switching losses due to FET capacitance is correct, but you are missing the gate driver switching current.

    IDD goes up to about ~12.1mA when switching at 5.1MHz/12V and no load. You can see how IDD goes up with frequency in figure 8 of the datasheet.

    When you add the 12.1mA*12V*2 to your 1.47W calculation, you achieve approximately 1.76W of power dissipation. 

    I'm afraid I don't understand your last question. Are you asking about paralleling the outputs together, or just turning them on and off at the same time?

    Both cases are okay in terms of power usage. The channels are both functionally isolated from each other and operate on their own input supplies. Our delay matching is good enough to allow paralleled outputs without increase in power usage. 

    See section 5 of this application note, which covers the performance of our dual-channel drivers with outputs paralleled.

    If this answered your question, could you please press the green button? If not, feel free to ask more questions.

    Thanks and best regards,

    John