Hi, Team,
Could you please check the attached waveform. Let me double check the SS timing. Is my understanding correct?
Best Regards,
Satoshi Yone
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Hi, Team,
Could you please check the attached waveform. Let me double check the SS timing. Is my understanding correct?
Best Regards,
Satoshi Yone
Yone-san,
Let me look into this.
Yone-san,
See the datasheet section 7.5.1.3.1. 4 msec SS time requires 9 x 0.95 = 8.55 msec delay from VDD_UVLO and EN_UVLO. Please increase the delay and remeasure.
Yone-san,
Tss is generally measured as the ramp time of the internal reference from the initial zero voltage to the final regulation voltage. There is typically a small amount of loop-delay between when the reference voltage starts to rise and when the output voltage starts to rise, to the exact rise time of the output voltage is typically slightly shorter than the programmed Tss time.