TPS544C20: STATUS_IOUT(7Bh)

Fujiwara,

1q. IOUT_OC Fault bit will be set if IOUT above IOUT_OC_FAULT_LIMIT only one time, correct? Or it will be set if device detects IOUT_OC_FAULT_LIMIT by seven times?

1a: The TPS544C20's current sense circuit detects the current flowing through the low-side FET at approximately the mid-point of the low-side FET on-time.  This current is sampled and held, then compared to the threshold set by IOUT_OC_FAULT_LIMIT.  That comparator feeds a 7-PWM cycle deglitch counter.  After the 7-PWM cycle deglitch counter over-flows, it will declare an Over Current Fault and set the STATUS bit.

2q. If IOUT_OC fault bit is set, PGOOD is also set "L"?

2a: PGOOD does not directly respond to IOUT_OC_WARN or IOUT_OC_FAULT.  PGOOD responds to VOUT_OV_WARNING and VOUT_UV_WARNING levels, but when the output starts to fall or stops switching in response to being disabled (CNTRL or OPERATION as set by ON_OFF_CONFIG) or in response to any fault condition with a shut-down fault response, PGOOD is forced low, even if VOUT  is between VOUT_OV_WARNING and VOUT_UV_WARNING.

3q. IOUT_OC warning bit is always set if IOUT_OC Fault bit has set? Or IOUT_OC Fault bit is only set even if IOUT above IOUT_OC_WARN_LIMIT?

3a: The TPS544C20 forces the IOUT_OC_WARN bit in STATUS_IOUT to be set if IOUT_OC_FAULT is detected, but the IOUT_OC_FAULT bit is only set if IOUT_OC_FAULT is detected.  The TPS544C20 does not allow the IOUT_OC_WARN_LIMIT to be set higher than IOUT_OC_FAULT_LIMIT, but due to tolerances in the analog detection, it is possible for IOUT_OC_FAULT to trip before IOUT_OC_WARN trips when they are set very close to one another.  In that case, the IOUT_OC_WARN bit will still be set.

4q. If IOUT above IOUT_OC_FAULT_LIMIT by very short time (less than PWM frequency), device can detect over current condition? (It means device can set STATUS_IOUT register.)

4a: The TPS544C20 detects IOUT_OC using the current flowing through the low-side FET during the low-side FET on-time and using a cycle by cycle sample and hold, it is not able to detect the output current contributed from the output capacitor and it can not respond to currents at frequencies faster than the switching frequency.

The slight exception to that is the Short Circuit Protection on the high-side FET. During the high-side FET on-time, the drop from VDD to SW is monitored.  If it exceeds the high-side short circuit protection limit, it will terminate the high-side FET on-time early to limit the high-side FET current, but this will not trigger  the IOUT OC FAULT status bit in IOUT_STATUS or a shut-down.  After 7 switching cycles the low-side IOUT_OC_FAULT limit will set the status bit and shut-down switching.