Other Parts Discussed in Thread: LM5145
(upper Fet )Specs says, Pin16 ( SW pin ) has absolute max limit = Vin. Basically once the upper Fet switches ON then the SW pin will see Vin and therefore the said Pin will always be at the 100% stress level.
This pin is also tied at the low side Fet where-in due to leakage inductance from PCB trace can potentially create additional spikes on top of Vin and will therefore see >100% stress.
Does in mean in order to use TPS40170 the design should be perfect/spikes is not allowed on the Vds of the lower FET because it should be equal to Vin, how do we do that??.
Even if the Body diode ( upper Fet ) clamps the spikes to Vin during OFF state ( lower fet ) it will still be "Vin + Body diode drop" and still > 100% stress.
Our company has internal voltage derating guidelines including stresses on every pins of the IC and 100% stress is not acceptable due to reliability reasons.
I think something is not right in how the absolute max is written for SW, can you check with TI experts on this please, I can't believe that it does not have upper tolerance limit, if there is upper limit, please advise the level such as absolute max for SW=Vim + given value? so we can really know the stress level on our side.
In our application, we are seeing "Vin + 5v for 5nS ) is this +5V/5nS spike on top of Vin enough to kill the part?
Please advise.
Thank You.
What can potentially fail in SW ckt if it sees >Vin??
Below is the specs: