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TPS7A4001: Max supported output capacitor

Part Number: TPS7A4001

In our Application,

Input Voltage = 65V

Output Voltage = 5V

Input Cap= 1uF

Output Cap= 10uF

R1= 100 K (//10nf)

R2= 30K.

We observe, some noise get coupled at output 5V & Feedback Pin, which causes drop in output voltage (Vout) till 2.5V.

The drop in Vout not observed with 100uF Capacitor at Vout. 

Is TI recommend to use 100uF/47uF capacitor at Vout?  

  • Hello Himanshu,

    The minimum output capacitor required for the TPS7A4001 is 4.7uF using a low ESR capacitor. 
    TI recommends using X7R or X5R dielectric capacitors.  To maximize AC performance you should use 10uF capacitors.

    What you are likely experiencing is noise coupling into the feedback pin of the linear regulator.
    Any noise that is coupled into this node will be magnified by the gain of the internal error amplifier.
    One of the symptoms of noise coupling into this node may be reduced output voltage, as you are experiencing.

    By adding a large output capacitor, you are introducing a low impedance path for AC noise to couple through to ground.
    A more robust solution is to try to identify the source of the noise, and then eliminate it.

    Two types of noise that are common in these types of issues are conducted noise and electric field coupling (also known as capacitive coupling) noise.
    Conducted noise has a shared impedance between the noise source and the linear regulator.  This could take the form of a copper trace.  A solution would be to characterize the noise then add a low pass filter (commonly an RC or LC filter) to eliminate it before it enters the LDO.
    Noise due to electric field coupling can occur from a noise source directly under the LDO within the PCB.  Ideally the LDO would have its ground directly underneath it on layer 2, which would act as shield against electric field coupling.  If a noisy signal is present there instead, such as high dV/dt switching noise or digital signals with fast rising edges, then capacitive coupling between the plane layers of the PWB will allow this noise to couple into the LDO.  A solution to this noise mechanism is more difficult.  Typical solutions involve slowing down the dV/dt of the noise signals (if possible), cutting traces in the PWB and routing the noisy signal around the LDO using twisted pair wiring, and in the most extreme cases a new layout is required to eliminate the noise coupling.

    Please let me know if you have any additional questions.
    If I have answered your question, please click on the "Resolved" link below. 

    Thanks,

    - Stephen

  • Hello,

    As per datasheet, "The TPS7A4001 device is stable with any output capacitance greater than 4.7 μF" 

    For My application, I have to use 100uF capacitor at output, 

    Please check and confirm,  the device will be stable at 100uF cap ( or 47uF output capacitor)?

    Thanks

    Himanshu

  • Hello Himanshu,

    Yes, the TPS7A4001 is stable with both 100uF and 47uF output capacitors.

    Thanks,

    - Stephen