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Original question:

LMG1210: Can I defeat the internal LDO?

LMG1210: lmg1210

user5327551
Intellectual 830 points
Part Number: LMG1210

Hi

  I am trying to build a hiend class D amp using LMG1210 and GanFet Mosfets

My question is about dead time. In your datasheet of LM1210 you have a time mismatch of 1ns nominal and max 3.4ns

   However the minimum R for dead time (PWM) is 0.8 nominal and 3.1ns max. By using the minimum R can you create a shoot-through in Mosfet from the above. Is that correct ?

Now using the HI LO input , you have no way of setting dead time. Does it mean it was eliminated (dead time)  if we use the HI LO drivepins  instead of PWM input ?

  • 0
    TI__Genius 12990 points

    Hi User,

    thanks for reaching out about LMG1210.

    When using LMG1210 in PWM mode (as found in section 7.3.3 of the LMG1210 datasheet) dead-time is set by 1210 to prevent the HO LO outputs from overlap and help prevent shoot-through. However shoot-through in the system is still possible if there is ground bounce or the miller turn on effect that turns on the gate of the complementary FET during switching.

    If using IIM or independent input mode (as found in section 7.4 of the LMG1210 datasheet) HI and LI need to be used to switch the output and the dead-time needs to be set by the controller.

    Each mode is standalone and pertains to the part operating in that mode. So the 1ns mismatch spec'd in the datasheet is for IIM however the 0.8ns dead-time spec is for PWM mode. So the mismatch for IIM is included in the minimum dead-time for PWM mode. The mismatch in IIM does not add to the min dead time. The mismatch in IIM is included in the dead time minimum. So in PWM mode better matching specs can be achieved.

    Does this help to answer your question? please let me know if you have any other questions.

    Check out the app notes below for even more detail

    Thanks,

     

  • 0 in reply to Jeffrey Mueller
    Intellectual 830 points

    If I understand this correctly , on PWM mode , dead time is set using Rext=1.78MΩ and its around 0.8ns. There should be no shoot through (unless ground bounces etc)

     

      In independent mode dead time has to be set before input to the LMG1210 at a minimum of 1ns (for no shoot through condition m unless ground bounces etc)

     

      Correct  ?

  • 0 in reply to user5327551
    TI__Genius 12990 points

    Hi User,

    Correct, however in IIM the inputs/outputs can overlap. The minimum dead-time is 0ns in IIM.

    thanks,

  • 0 in reply to Jeffrey Mueller
    Intellectual 830 points

    Hi

      so you are suggesting the output/inputs in independent mode both need a 1ns delay ?

    At last the LMG1210 has 1.5A peak source , is that on both H and L outputs simultaneously ?

  • 0 in reply to user5327551
    TI__Genius 12990 points

    Hi User,

    Thanks for your follow up question,

    The propagation delay (input to output delay) for PWM mode and IIM is very similar. You can use LI/HI in independent input mode however the LI/HI inputs do not require a delay (unless a dead-time is needed in IIM).

    Each LMG1210 high-side and low-side driver outputs (HO and LO) is capable of a 1.5A source current for charging the gate for a fast rise time and 3A sink current for discharging the gate for a faster fall time and to help with miller effect.

    let me know if this helps answer your questions and feel free to ask any other questions.

    Thanks,

  • 0 in reply to Jeffrey Mueller
    Intellectual 830 points

    Hi Jeff ,

      my mistake , I am not asking about propagation delay but for skew .

    So in PWM my dead time needs to be higher than 0.8ns to no shoot through can happen

    In IIM mode my dead time needs to be higher than 1ms for the same.

       Now , in the datasheet we can see those values are "typical". Maximum values are 3.4ns and 3.1ns

    Since I am using full bridge configuration for my design (so 2 LMG1210 controllers) does it mean that my deadtime should be at least 3.4ns (in IIM mode) and 3.1ns in PWM mode for no shoot through ?

  • 0 in reply to user5327551
    TI__Prodigy 645 points

    Hi,

     First, to clarify, in PWM mode with maximum resistance (1.78M), the dead time for the outputs when unloaded is 0.8ns. The critical spec is of course that it can be -0.5ns which means that for a hypothetical FET connected to unloaded output, there could be 0.5 ns of shoot-through. I said hypothetical because in reality all fets load the output. Loading the output has a tendency to increase the effective dead time because the pull-down current (3A) on the LMG1210 is higher than the pull-up current (1.5A) which means the fall-time is faster than the rise time. This asymmetry effectively adds dead time which has a larger effect with increasing load capacitance and is the rationale for why the minimum dead time is so short. For some applications with large gate capacitance, even the minimum dead time setting results in a large enough effective dead time to be used. For small FET applications, some small additional dead time is probably required to stay away from the negative dead time which results in shoot-through. 

    As a practical recommendation, I'd recommend you set your system up in the lab, look at the effective dead time either by looking at the switch node or looking at the gate waveforms, and then adjust the dead time control resistor make sure you have nominally at least 2.3 ns dead time effectively. The 2.3 ns should be enough to correct for any variation of the dead time that the LMG1210 will have part to part. (I'm getting this from the 3.1-0.8 datasheet numbers as a "max deviation from the typical" value) If used in IIM mode, I'd have at least 3.4 ns of dead time to correct for maximum variation.

    Nathan

  • 0 in reply to Nathan Schemm
    Intellectual 830 points

    Great answer.

      Last question , my FET has 7nC gate capacitance (total) with variance of 30% max from part to part

      How much more (if any ) should I increase dead time. I am calculating 1.5ns with 1.5A  (with enough capacitance next to LM1210)  can you confirm

  • 0 in reply to user5327551
    TI__Prodigy 645 points

    By my calculations, 20% of the rise time for that FET would be about 1.5ns or so, so that would a good amount to correct for the capacitance variation.

    However, a bit more than that may be in order because the drive strength of the output varies. Because both the pull-down and pull-up FETs are on the same die, they maintain about the same 2:1 ratio of pull-down to pull-up current, but the actual current does vary over temperature and part-to-part, therefore the rise and fall speed varies as well. So both the rise and fall time can be from 2/3*nominal to 4/3*nominal, but the rise and fall speed will generally track with each other over temp and part-to-part. I'd look at the rise an fall times on a scope and then analyze what would happen with faster and slower times. Alternatively, since most of the change will occur over temp, operating the circuit at cold and hot temps and comparing the rise and fall times would be instructive as well.

    Regards,

    Nathan