CCS/UCD3138A: Design/Code for integrating secondary DPPs into VSENSE primary DPP

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Hello,

what is topology for this project? Is it TI EVM or your board?

Thanks,
Sean

Hey Sean (and Yitz),

This is a custom board using the 3138A and (from my hardware guy) mostly reference circuitry around it. From my understanding it is a fairly straightforward flyback power supply. So, we are taking in 110VAC @400Hz source and must very tightly control/source 28VDC.

So, we have VSENSE feedback tied into AFE0, ISENSE feedback tied into AFE1, and an IPK circuit tied into AFE2.

I have the general ramp up/down and regulation of 28VDC working great utilizing AFE0 / VSENSE. Been dialing in and learning about where the ISENSE line sits and getting a good feel for it. BUT, I really don't know how/where to try to feed the EADC, Filter, or PWM from AFE1 / ISENSE.  Does that question make sense?

Anther way to say it is that I've got 2 more control chains than I need. But assume they are there to serve a purpose. Just need some advice on what I should be doing with them!

NOTE: I can more than likely attach a diagram if it helps. As long as this post is tagged as private. I remember there used to be a difference between "public" forum posts and "private".

Hi, Dan,

I think I know your structure. The first loop is used for voltage loop to regulate output voltage tightly; the second loop is used for current loop to achieve constant current, The third loop is used for peak current control. I am not sure if you are using voltage mode control or peak current control. You can get some information from EVM user guide of UCD3138PSFBEVM-027, available on the website.

Regards,
Sean

Sean,

All that sounds right. The problem is that the VSENSE flyback on DPP0 controls DPWM0, which does the actual regulation/control.  So, can ISENSE be used to make adjustments to the DPP0 chain? Automatically? Or code that monitors ISENSE's EADC and "bumps" the REFDAC on the VSENSE control line?  I'm not seeing how I can integrate the information gathered by the ISENSE circuit (DPP1) into the control chain that dictates the output DPWM0 waveform??

And what does the IPK (peak current) on DPP2 do? Is it set to trigger a fault via the FAULT_MUX? Something that will trigger a full shutdown of the DPWM0 (thus the power supply)??

Thanks for the quick answers. They are definitely helping me to start understanding how to use the hardware and peripherals the UCD3138A has available.

Sean,

A little more detail/answers to the above. The power regulation is done by DPWM0. This is loop_mux'd to be from the VSENSE feedback. This process works great currently.

The ISENSE line is (in theory) there to be able to see load change event happen faster than the VSENSE will. The power supply is a constant voltage regulator. Externally we will have large current load swings. I.e. 1.5A -> 2.5 A -> 4.0A -> 1.5A -> 0.5A.  So, what I'm trying to accomplish is reacting (quickly, or quicker) to the load changes by having DPP1 (ISENSE) setup to give me a warning that a load change is happening. That's where my questions lie.

Once I see a large delta (or even a SAT_LOW) on the EADC from DPP1, can I provide a "kick" to the REFDAC of DPP0? Is this safe to do? DPP0 is setup to allow the Filter0 to keep control of REFDAC. Is it standard design template to interject the events from one DPP into another, such that the DPWM0 is ultimately adjusted as quickly and efficiently as possible?

IPK is another issue that I haven't even gotten around to yet. I'll get into that as soon as we land on a solution for ISENSE (DPP1). Thanks!

Hi, Dan,

I am not sure if your board adopts peak current mode control. You have all information. output voltage, load current/secondary side current, and primary side current.

The second loop(EAP1) is used for constant current control. When load current is higher than max load, the current command will take over from the voltage loop and modulate the DPWM duty to accomplish current limit. It is not used for for normal load transient.

 The third input is primary side current. If it is peak current mode control, the voltage loop output is connected to FE2's DAC. It is like a nest loop. You can refer to PWR-027 (PSFB EVM) user guide to find more details.

Hopefully, it helps.

Regards,

Sean