TPS650864: [TPS6508641] Some questions

Hi Geonwoo,

Thank you for your questions. I've included answers below.

1. VTT LDO output is 0.9V. But according to Xilinx datasheet, VPS_MGTRAVCC input range is min 0.825 typ 0.85 max 0.875.

I think i need a external LDO for voltage drop from 0.9V to 0.85V.

Can i add LDO in external next to VTT LDO?

[Kevin] Yes, use of an external LDO is the recommended solution from Xilinx after they decreased voltage on VPS_MGTRAVCC. My understanding is that 0.9 V works as well, but that they only recommend 0.85 V. The Ultra96 board designed by Xilinx used 0.9 V without issues and Xilinx decided to release it with 0.9 V rather than redesign it when the specification was updated to reflect the lower power requirements.

Alternatively, you could use TPS650861 (user programmable version of TPS650864), use the TPS6508641 OTP Generator, and change the program to have LDOA3 as 0.85 V. 

2. We have to enter the power associated with GTH.

Accroding to Xilinx datasheet, VMGTVCCAUX is 1.8V, VMGTAVCC is 0.9V and VMGTAVTT is 1.2V.

Can i connect VMGTVCCAUX to BUCK6?

Can i connect VMGTAVCC to VTT LDO?

Can i connect VMGTAVTT to LDOA3 or LDOA2 or BUCK5?

And let me know if i add filter or not.

[Kevin] Based on Figure 1-4 in the Xilinx Ultrascale+ Design Guide, they recommend shorting VMGTVCCAUX to VPS_MGTRAVTT (LDOA1), VMGTAVCC to a new rail (VTT LDO should work in this case since it powers up before LDOA3), and VMGTAVTT to VCC_PSPLL (LDOA2, however I would recommend using LDOA3 here based on the sequencing requirements in the Xilinx datasheet page 16). I don't see filters on any of these inputs in the diagrams provided by Xilinx.

3. If i use VCCO_HPIO to 1.8V, which of SWB1_2, BUCK6, LDOA1 should i select? 

[Kevin] LDOA1 or SWB1_2 would be best if they can provide enough current for your design. BUCK6 powers up before VCC_PSPLL which is not recommended.