WEBENCH® Tools/UCC256302: Key parameter for FET selection

Ryo Akashi

Genius 9470 points

Part Number: UCC256302

Tool/software: WEBENCH® Design Tools

Hello experts,

I have question for FET selection of power design which use UCC256302.

In datasheet 7.2.2.13, there is description "The slew detection circuit has a detection range of 1V/ns to 50 V/ns."

For this detection range, what electrical characteristic of FET should I take care?

Thanks and best regards,

Ryo Akshi

over 6 years ago

0 Benjamin Lough over 6 years ago

TI__Mastermind 27105 points

Hi Ryo,

Smaller Coss MOSFET is preferred in order to keep the switch node slew rate >1V/ns. Section 7.2.2.13 touches on this topic. The resonant current at gate turn off is used to drive the ZVS switching transition. To reliably detect the slew rate, the switch node must have a dV/dt faster than 1V/ns. If the remaining resonant current at gate turn off is known, the maximum switch node capacitance can be calculated. Since this is a half bridge configuration with two MOSFETs, I would suggest selecting MOSFETs with Coss<1/2 of the calculated maximum switch node capacitance to ensure proper slew rate detection.

Best Regards,

Ben Lough

0 Ryo Akashi over 6 years ago in reply to Benjamin Lough

TI__Genius 9470 points

Hello Ben,

Thank you for your reply.

Let me confirm the detail of your comment.

You mean FET's Coss (red script) should be smaller than half of maximum switch node capacitance (blue script, which is made by pattern?).

Is it correct?

Thanks and best regards,

Ryo Akashi

0 Benjamin Lough over 6 years ago in reply to Ryo Akashi

TI__Mastermind 27105 points

Hi Ryo,

The maximum switch node capacitance includes the Coss of both FETs plus any parasitic capacitance from the PCB pattern. Each MOSFET Coss should be less than half the total allowable switch node capacitance.

Best Regards,

Ben Lough

0 Ryo Akashi over 6 years ago in reply to Benjamin Lough

TI__Genius 9470 points

Hello Ben,

Thank you very much for your reply.

I understand about maximum switch node capacitance node includes FET's Coss and capacitance from PCB pattern.

In previous reply, you mentioned that

"If the remaining resonant current at gate turn off is known, the maximum switch node capacitance can be calculated"

Do you have any app note or document for this calculation?

Thanks and best regards,

Ryo Akashi

0 Benjamin Lough over 6 years ago in reply to Ryo Akashi

TI__Mastermind 27105 points

Hi Ryo,

Equation 40 in the UCC256302 datasheet contains the calculation. For estimating the resonant current at gate turn off, I would suggest using power stage designer. The tool can plot the resonant current for a LLC power stage. From the graph, use the resonant current information when the gate turns off to determine the maximum allowable capacitance. http://www.ti.com/tool/POWERSTAGE-DESIGNER

Best Regards,

Ben Lough

0 Ryo Akashi over 6 years ago in reply to Benjamin Lough

TI__Genius 9470 points

Hello Ben,

Thank you very much for your reply and suggestion.

Resonant current at gate turn off is as below?

Thanks and best regards,

Ryo Akashi

0 Benjamin Lough over 6 years ago in reply to Ryo Akashi

TI__Mastermind 27105 points

Hi Ryo,

The resonant current at gate turn off is where the discontinuity happens in the resonant current

Best Regards,

Ben Lough

0 Ryo Akashi over 6 years ago in reply to Benjamin Lough

TI__Genius 9470 points

Hello Ben,

Thank you for your reply.

I understand how to estimate the resonant current.

Let me confirm one thing about Coss.

You advise me to select the FET which has the Coss less than half of maximum switch node capacitance.

Less than half means that this topology use two FETs, so majority of capacitance value come from these two FET's Coss.

So we need to select the FET (Coss<1/2 maximum sitch node capacitance) as you advised me.

Is it correct?

Thanks and best regards,

Ryo Akashi

0 Benjamin Lough over 6 years ago in reply to Ryo Akashi

TI__Mastermind 27105 points

Hi Ryo,

Your understanding is correct.

Best Regards,

Ben Lough

0 Ryo Akashi over 6 years ago in reply to Benjamin Lough

TI__Genius 9470 points

Hello Ben,

Thank you for your reply.

I understand.

Thanks and best regards,

Ryo Akashi

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WEBENCH® Tools/UCC256302: Key parameter for FET selection