As attached, Vbus is the 24V DC_PWR in。During PWR ON/OFF test ,the tps43060 will be damaged after 1500 test round.
We wonder that if there is some advisement to solve this problem,TKS sincerelysys_attachment.pdf
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As attached, Vbus is the 24V DC_PWR in。During PWR ON/OFF test ,the tps43060 will be damaged after 1500 test round.
We wonder that if there is some advisement to solve this problem,TKS sincerelysys_attachment.pdf
Hello,
Thank you for posting. I thought I replied yesterday, but somehow my reply may not get through. There no obvious clue in your schematic to tell how this happened. To help us better understand the issue, could you send some key waveforms like the SW node, Vin and Vout during the PWR ON/OFF test. Both overview and zoom in scope pictures are needed.
Please also provide the following info:
Thanks,
Youhao Xi, Applications Engineering
Hi ,Youhao
First of all,TKS for your attention.According to your suggestion,some key waveforms were captured.
There is some info for your concern below:
(1)As shown in the Input_Zoomin,the input voltage rise from 5V to 20V cost about 1.5ms.
(2)During the test,The Vout was cut off by the MOSFET Q27,Thers is almost no load.And the quantity of electricity will be storaged by the Ultra-large capacity capacitor all the time.
(3)During the test,the On-time was 46 seconds,and the Off-time was 6 seconds
Thanks
Hi,
Thanks. I am trying to understand these waveforms. Why it is so noisy? May I bother you to do the following tests:
(1) startup by input voltage application. I need to see at the time scale of 1ms/div. Monitor Vin, Vout, and SW. two waveforms, 0A and full load.
(2) step load response. After the circuit operate, please do the step load test, and let the load current to change from 0A to full load, and also 50% load to full load. Make the step load 50% pulse width, namely high load for 5ms, and low load or no load for 5ms, repetitive. Monitor Iout, Vin and Vout. Scope time scale 5ms/div. Vout signal ac coupling.
Thanks,
Youhao