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Internally Compensated Buck Converter Stability with Bulk Load Decoupling

Hi,

I'm designing a power supply for a FPGA and the recommended decoupling capacitance for the core voltage rail is very large (~1mF)  when compared to the output capacitance on the buck converter (10uF).

1.) Will the decoupling capacitance required by the FPGA change the pole frequency of the LC filter and effect the stability of an internally compensated buck converter?

2.) If there is an issue with stability how would I resolve this issue?

  • The input capacitors of downstream components can affect the stability of the converter. The impedance between both banks of caps is what ultimately devices whether or not it will play a huge role. Keep in mind, the capacitance of most input caps can often be much smaller than the output capacitance of a buck, so the effect may be negligible. Getting an accurate model of the power design may be one way of determining the stability of the converter, but the ultimate test would be design verification on a prototype board.

    A large capacitive load will require some additional thought when setting the soft-start of the converter. Please reference datasheet of your specific converter for this.

    Output power stage in addition to the feedback network play a role in loop response. Theoretically, if you were to add a lot of output cap, you would pull in the bandwidth of the converter. If you would want to mitigate this, you could add a feed forward cap to increase bandwidth and improve phase margin at the crossover frequency. If you were to balance output cap and converter bandwidth, you could build a design whose overshoots and undershoots are small while still being very responsive to high-frequency transients.

  • Hi,

       Also you can take a look at this portal to get power recommendations for specific FPGAs.

    http://www.ti.com/design-resources/design-tools-simulation/processor-fpga-power/overview.html

    Regards,

    Gerold