Hi,
I'm designing a power supply for a FPGA and the recommended decoupling capacitance for the core voltage rail is very large (~1mF) when compared to the output capacitance on the buck converter (10uF).
1.) Will the decoupling capacitance required by the FPGA change the pole frequency of the LC filter and effect the stability of an internally compensated buck converter?
2.) If there is an issue with stability how would I resolve this issue?