UCC28950: About Hard switching operation

Hello Yusuke

The UCC28950 and UCC28951 are controllers for the Phase Shifted Full Bridge topology. This means that they have a delay between OUTA and OUTB and between OUTC and OUTD, the delays are necessary to allow for the Zero Voltage Switching transitions to take place.

If the user wants to hard switch the bridge then they can minimise the TABSET, TCDSET times by using 13k resistors at DELAB and DELCD and tying the ADEL pin to VREF through a potential divider - here's an outline of how this would be done. /cfs-file/__key/communityserver-discussions-components-files/196/8308.Calculating-Adaptive-Delays.pdf

A similar approach can be used to manage the SR delays.

Turning "OUTA and OUTD" and "OUTB and OUTC" on at the same time implies operation at Dmax. This can be achieved by tying EA- to GND. If EA+ is tied to VREF/2 then this will set COMP high and the controller will run at Dmax indefinitely.

Operating continuously at Dmax is allowed - the controller will not regulate the output voltage because the duty cycle is fixed but otherwise there should be no problems.

Operating with hard switching will increase losses significantly - especially on high input voltages. This is ok if the designer can accept the reduction in conversion efficiency and the increased heat losses in the switches.

The dv/dt rates in hard switching will be significantly higher than those seen in a soft switched application (ie, with ZVS) and this will increase the conducted and radiated noise signatures unless additional care is taken in layout and filter design.

I'd be interested to understand why the customer wants to use this controller for hard switching - I think it makes more sense to take advantage of its full capabilities and use the delay times to achieve ZVS..

Regards