BQ76940: ADCGAIN2

Hi User,

From the question the waveform looks like the signals shown might be 2 byte reads with the cursor at the slave driving data low for the ACK of the address.  Wrong image data 0x23 ACK, 0x22 NACK.  Correct image data 0xA3 ACK, 0x22 NACK.

If the address was 0x59 it does not make sense, the register should be a fixed value. 

The difference in the falling edge of SDA just before the ACK should not be significant since clock is low, but you might look to see if there are other edges which may be causing some problem on the bus. One technique is to put in a series resistor so that when low you can tell which device is driving the bus.  The rising edges seem ok although the clock rises faster than data.

The clock at the fastest looks like 2.5 cycles in 10 us, or 4us/clock or 250kHz.  The maximum specification for the BQ76940 SCL is 100kHz or 10 us/clock.  If you have already checked the addressing you might slow the interface clock rate to specification to see if the data becomes consistent.  

If it is not one of these please check again.