Figure 29 shows a 20 ms startup time with no capacitance on CNR/SS. Is this correct or should the plot include an event trigger at t = 20 ms (i.e. enable asserted, input voltage applied)?
Based on information in other parts of the datasheet, I’m don’t think the startup time is really 20 ms for this condition but if I only looked at Figure 29 I would think it was.
Thanks,
John