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BQ25150: LP pin response time (BQ25150/ BQ25155)

Part Number: BQ25150

How quickly does the LP input react to level changes? In particular, does the pin reliably tolerate a low level pulse of 128us without entering the low power mode?

As you might have guessed I plan on connecting the INT pin and LP pin together. This allowes me to use all required features of the part without HDI technology.

Thanks for your help.
Dennis

  • Hello Dennis,

    Do you intend to use the ADCIN function? If not, i'll suggest connecting ADCIN to /LP which allows you to have control over when you go into low power mode. I'm assuming you don't intend to use Via-In-Pad.

    Also can you please share your current sample layout.

  • Thanks for the quick answer, Raheem.

    Raheem said:
    I'm assuming you don't intend to use Via-In-.

    On fine pitch parts this is called HDI and costs 10x as much as a normal PCB which is unfortunatly a dealbreaker.

    Raheem said:
    If not, i'll suggest connecting ADCIN to /LP which allows you to have control over when you go into low power mode.

    That was exactly my idea. The MCU operates at 1.8V so it is well within the 1.95V absolute maximum voltage of the ADCIN pin.

    However I'd also like to use the INT pin, which is harder to route out. My ideas are:

    1. Enable the LP pin with an internal pullup (100kohm) of the MCU. At the same time that pin could be an input, to detect the INT signal, if it was shorted to the LP pin. However I fear the BQ25150/5 to enter low power mode. Therefore the question is whether the pulse would be ignored.
    2. Connect the INT pun to the MR pin. The obvious downside is that I can not detect a INT pin low level if the button is pressed, but this is a rare case and the registers could be polled. Worse is the pullup to BAT, the maximum charge voltage of 4.25V tricky to connect to the MCU. If the PG pin mirrors the MR pin (ICCTRL1: PG_MODE_1 = 2b10), is it quick enough to catch the 128µs pulse?

    Open questions marked bold. (Sorry to bother you this much, but I can't easily test a BGA part myself)

    Greetings

    Dennis

    PS: I've also attached a mock-up of how the layout could look like. Minimum copper/clearance is 0.1/0.1mm. Of course, in the final application parts might be re-arranged a bit. GND plane is missing right now, but will be added for final version. traces at bottom are input/ output signals to MCU and button.

    Note this layout shows INT connected to LP, option 2 would be to connect INT to MR.

  • Hello Dennis,

    You can prevent the device from entering low power mode by holding /MR low and setting the MR_LPRESS_ACTION bit in 0x36 to 2b01 so the device does nothing when the /MR pin is held low when in BAT only mode.

  • Your answer doesn't answer either question.

    In the meantime I found an acceptable solution without relying on undocumented behavior by changing the footprint slightly.

    You can mark this question as closed.