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Original question:

LMZM33606: Negative output with External Sync Clock

LMZM33606: Negative output with control pin consideration

PingL
Prodigy 170 points
Part Number: LMZM33606

Hello,

I would like to design +15V input to -15.5V 2.5A output with external 1MHz sync clock input with default RT set to 1MHz self switching.

In IBB application, TI provide design consideration on EN pin and PG pin also with Sync pins design consideration confirmed in this forum.

Now I am worry about others control pins like SS/TRK, RT and BIAS_SEL is there any design consideration require. Because the reference (PGND, AGND) are moving toward negative voltage after enable.

- SS/TRK connected to -14V5 output (AGND pin) with ceramic capacitor to control soft-start time. (Equation 6)

- RT connected to -14V5 output (AGND pin) with 38K3 to set internal Fsw to 1MHz. (Table 6)

- BIAS_SEL connected to -14V5 output (PGND pin) to disable internal BIAS LDO. Not sure which voltage should be provide to increase efficiency.

Best regards,

Ping

  • 0
    TI__Guru 50120 points

    Hi Ping,

    As you have mentioned in your post, the device return path pin (PGND and AGND) is now the negative output voltage and the device output pin (VOUT) is now system GND. Note that since all the control signals of the buck is referenced to its ground terminal, this means that these auxiliary functions must be level shifted to system ground if they are to be utilized (Reference Section 7 of  SNVA856). This is the case for EN,PG and SYNC.

    However the voltage stress on the pin of SS/TRK and RT will remain same for both buck and inverting buck system. The voltage difference between SS/TRK to GND of a buck will be the same as the voltage difference between SS/TRK to NVOUT(GND pin) in an inverting buck because it is connected to the same node/ return path. In this case, SS/TRK and RT will be within the voltage threshold and not exceed absolute max voltage on the pin with respects to the return path in both buck and inverting buck configuration. In the device's point of view, the voltage on the SS/TRK and RT will always be greater than the return path. While in buck configuration the values will be positive, in an inverting buck configuration the values will be negative.

    For the BIAS_SEL case, if you connect the BIAS pin to the system GND (device VOUT pin) this will enable the improved efficiency. If you connect BIAS pin to nVOUT(device return path)  the bias feature will be disabled.

    Regards,

    Jimmy

  • 0 in reply to Jimmy Hua
    Prodigy 170 points

    Hi Jimmy,

    Great! Thank for your advice on BIAS_SEL connection for efficiency improvement without additional supply resource.

    At last, I think is no harm to following datasheet recommend to isolated AGND connections locally on IBB application. Although AGND & PGND pins are now NVOUT, but in a device point of view that remain a "virtual ground" reference.

    (i.e. AGND pins connect with SS/EN/RT pull resistors and capacitors connection, and leave AGND connection back to PGND from module internally)

    When I play with Webench, the generated schematic for IBB application does wire connection between AGND and PGND, which is different from generated buck application schematic with AGND PGND isolation.

    Thanks & regards,

    Ping

  • 0 in reply to PingL
    TI__Guru 50120 points

    Hi Ping,

    That is correct. Do not connect the AGND pin to PGND since this is already made internal to the device.

    Regards,

    Jimmy