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TPS55340: TPS55340 Layout checking

Part Number: TPS55340

This is the current schematic I use. I use TPS55340PWPR.



The WEBENCH recommended me to use B560C-13-F 60V Schottky diode and the 4.7uH XAL5030-472MEB inductor.

All the resistors have 0.1% tolerance with 1/8W Power rating and 0603 (16mm x 08mm) size.

I removed the "thermal relief" (polygon trace) to swallow the GND pads. I placed

CIN: C2 10uF + C4 10uF + C3 15uF

COUT: C7 470nF + C8 470nF + C9 10uF

with vias.

R1, R2, R3 is used for the feedback loop and I referred  PMP15037 (DAC signal to decrease VOUT)

Top (FR-4, 1.6mm thick 2 layered PCB)

Bottom

Does the layout look fine? Do I need more vias?

  • Hi David,

    Before I look through the layout and give you comments, I have several things want to confirm with you: What does the input comes from? Why the vin range is 2.8V to 5.15V. And what's the maximum output voltage that you want? Considering the maximum duty cycle limit shown as below, the maximum output voltage will be limited by the maximum duty cycle 89% and minimum operating input voltage.

  • Hi, Zach

    The input will be either

    1. USB 5V

    2. Single Cell Li-ion 3.7V 500mAh

    My desired max output voltage is 38V. By using PMP15037, I will control VOUT from 6V to 38V.

    Zack Liu said:
    Considering the maximum duty cycle limit shown as below, the maximum output voltage will be limited by the maximum duty cycle 89% and minimum operating input voltage.

    - May I ask you about the meaning of this duty cycle limitation, please? Curious whether there is an equation between the input voltage and the duty cycle.

    - Will using a single cell Li-ion battery with a capacity lower than 500mAh become a problem?

    Hope the VIN is okay with this.

    - Thanks for providing the PCB comments, as well.

  • Hi David,

    For a boost topology, the Vout to Vin equation is D=1-effi*Vin/Vout.

    Assuming the minimum input voltage is 2.8V and efficiency is 0.85, duty cycle=1-0.85*2.8/38=93.7%, which is higher than the maximum duty cycle limit spec(minimum) 89% (extreme conditions). That means when li-ion battery voltage decreases down to 2.8V, due to the maximum duty cycle limit, the output voltage will not go up to 38V, approximately only 22V.

    Using 89% as Dmax, the minimum operating input voltage to generate 38Vout Vin=(1-Dmax)*Vout/effi=(1-0.89)*38/0.85=4.9V. 

    In summary, only the input comes from 5V USB, you could get 6V-38V Vout. If input comes from the single cell Li-ion battery, you could get 6V-22V Vout in extreme conditions.

  • Thanks for the clarification.

    - Does the Li-ion's capacity 500mAh matters as well?

    - Can you check my PCB layout, please? More vias needed?

  • Hi David,

    Li-ion capacity decides the lifetime and maximum discharge current. You need check the maximum discharge current with battery factory.

    For layout, below are my comments:

    1. Input caps, inductor L, Diode locations are good. Please change output capacitors C7, C8, C9 locations close to the IC. Look the picture below, I place C7 more close to IC and the GND pins of IC are connected to C7, C8, C9 negative pads directly. The parasitic inductors of PCB could be reduced in such way. 

    2. Put smaller value Cout more close to IC because ceramic caps has lower impedance.

    3. Vias near the negative pad of input caps and output caps are good. 

  • Thanks, Zack. Like this?

    I lowered the output voltage to 22V using your advice. Also, the output capacitor is closer to the IC now.

    The WEBENCH is telling me to use

    - two 1uF ceramic C7, C8

    - one 10uF Electrolytic Capacitors  C9

    Zack Liu said:
    Put smaller value Cout more close to IC because ceramic caps has lower impedance.

    Q1. You mean move 1uF (C7, C8) close to the boost converter as possible, not the 10uF since 1uF is a low impedance ceramic capacitor?

    Q2. Considering the size, do I really need to use a 10uF Electrolytic Capacitor or can I replace this to a 10uF ceramic type?

    The above layout is using a ceramic 10uF. Hope I can know the reason why I must use at least one Electrolytic Capacitor.

    Zack Liu said:
    Look the picture below, I place C7 more close to IC and the GND pins of IC are connected to C7, C8, C9 negative pads directly. The parasitic inductors of PCB could be reduced in such way. 

    Q3. May I ask what you've meant by this; close decoupling capacitors decrease the parasitic inductors of PCB?

  • Hi David,

    The layout looks much better now. R1 must be the feedback resistor. Please put this one close to R2, R3 and IC will be better.

    Below are my comments:

    Q1: Yes. Put one 1uF ceramic capacitor close to IC is enough. If you choose two ceramic capacitors with the same size, DC rating and look at their datasheets, you will find lower value ceramic capacitor has lower impedance at high frequency range.

    Q2: I suggest you use ceramic capacitor because it has lower ESR compared to electrolytic capacitor. Use one or two 10uF capacitor. Take care when evaluating a capacitor's derating under DC bias.

    Q3: You should know that the PCB has parasitic inductance. The parasitic inductance between the negative pad of output capacitor and GND of IC will cause high spike during switching because the high side switch current is discontinuous.