LM5069: Regarding clarification on Timing capacitor & current limit

Hi Balaji,

Can you please share schematic, layout files and filled up design calculator. The design calculator is available at http://www.ti.com/product/LM5069/toolssoftware

Instead of step-load, can you check by increasing the load current gradually where the controller trips.

BR, Rakesh

Dear Sir,

Schematics is simulated under short circuit condition using TINA-TI software and observed result (Restart sequence and Load current during fault timeout period) is attached here.
From the simulation result, it can be observed that our prepared schematics gives expected result.
i.e. 1. Short circuit Current (14A) is allowed during fault timeout period. But our chosen Rsense value should allow 18.33A as per the datasheet information (55mV/3milliohm).
2. Seven cycles of Charging and discharging of timing capacitor occurs for restart time of 19.8 seconds after fault timeout period.
During restart time MOSFET is kept off as mentioned in the datasheet.

But when schematics is tested in practical the above points is not observed (results are attached in the previous message).

Kindly clarify the reason and give solution.

Hi Balaji,

Sure. Please provide below details to debug the issue.

What is the set value of power limit ?

Can you share schematic, layout files and filled up design calculator. The design calculator is available at http://www.ti.com/product/LM5069/toolssoftware

The following videos covers how to use the Design Calculator.

https://training.ti.com/node/1133677

https://training.ti.com/node/1133673

https://training.ti.com/node/1133664

https://training.ti.com/node/1133681

Instead of step-load, can you check by increasing the load current gradually where the controller trips.

BR, Rakesh

Dear Sir,

Power limit set value is 89.3W (Calculated using Equation 9 given in page no:20 of LM5069 datasheet)

Rsense= 3milliohm
Rpwr= 30000 ohm
Vds= 31.5V (Vin max)

Schematics is tested by gradually increasing the load current, it trips at 18A as shown in below figure. But after fault timeout period (100 ms), restart time of 19.85 seconds is not observed.

Schematics is also shared here. Kindly clarify the reason for

1. why there is no expected restart time (19.85 seconds) is observed.

2. During fault timeout period only 3 A is allowed instead of allowing 18.3 A (for selected Rsense=3 milliohm) under short circuit test.

Manufacturer part no of MOSFET Q3 is PSMN4R8-100BSEJ
DNM represents DO NOT MOUNT Components

Dear Sir,

When schematics is tested by gradually increasing input voltage from low voltage to 31.5V & above, result observed is as expected.

But when it is tested with input of 31.5V & above (at start itself), LM5069 asserts the condition as fault & restarts with time interval of 10.8 seconds.
Actually there is no fault,i.e 1. set value of undervoltage & overvoltage is 5V & 57.5V respectively. 31.5V input voltage is within the limit. 

                                                 2. Load applied is 3ohm, so load current will not be exceeding 10.5A (31.5V/3ohm). Load current(10.5A) is within the set limit 18.33A(55mV/3milliohm).
                                                 3. Also Fault is not due to set value of MOSFET power limit. Pmosfet= Vds*Ids [Vds=(Rdson=4.8milliohm)*(Ids=10.5A)] ; [Ids= 10.5A] So Pmosfet will not exceed 0.529W.

Then Why LM5069 asserts the condition as fault eventhough there is no fault condition. Observed result is attached below (yellow-Timing Capacitor; Pink-Load current)

Kindly clarify the above observation.

Hi Balaji,

With Power limit of 89.3W and at Vds= 31.5V, the device limits the current approximately to 89.3W/31.5V = 2.835A during recovery from overload fault.

What is the load when you directly apply 31.5V. It has to be <2.835A to make successful startup.

Are you sure about the timer cap value? Is it electrolytic or ceramic type ?

BR, Rakesh

Dear SIr,

when 31.5V input applied , load is 3ohm (31.5V/3ohm=10.5A). From your statement, I understood that Load current is exceeded the device limit value of 2.835A.
But the device limit current value will be 2.835A only under short circuit condition right? , Not for overload or other faults right?
i.e. Under overload condition,
Vds will be Ids*Rds right? So 89.3W/Vds will reach current limit value of 18.3A (by Rsense). It should allow 18.3A during fault timeout period considering Plimit also. But we have observed only 3A during Tfault. Why it is So? And why 3A current pulse is repeating after fault timeout period. Observed result attached in e2e.ti.com/.../3105415

Also You have stated that When 31.5V input applied at start, load current should be <2.835A for successful startup.
But when input of 28V is applied at start under full load condition (9A), 9A load current is allowed LM5069 successfully startsup & works fine. Here (89.3W/28V= 3.18A) current limit for startup doesn't play thr role right?. Because Vds drop is only Rds*Ids not 28V.
In this case, for applied 31.5V input  under full load condition why LM5069 asserts the condition as fault.

Timing Capacitor used is Ceramic (CAP CER 2.2uF 50V 10% 1210 X7R 2.80 mm RoHs) Manufacturer part number:C3225X7R1H225K250AB
Clarify why we are getting lesser restart time in practical (under short circuit test & Overload test). In simulation result we observed the expected Restart time.

Kindly clarify the above points.

Hi Balaji,

The device operates in power limit mode during startup, restart mode (recovery from overload fault also) where the VDS across the external FET is high (close to full Vin voltage).

But when input of 28V is applied at start under full load condition (9A), 9A load current is allowed LM5069 successfully startsup & works fine. Here (89.3W/28V= 3.18A)

What is the type of load? Is it 28V/9A = 3.111 Ohm ?

We can expect some variation in restart time from device to device as the fault detection and sink currents has tolerance. Is it matching if you consider 120uA, 3.75uA values. ?

BR, Rakesh

Dear Sir,

The device operates in power limit mode during startup, restart mode (recovery from overload fault also) where the VDS across the external FET is
high (close to full Vin voltage).

Can you please elaborate how Vds is equal to Vinput under overload condition & startup mode. What I understood is that under overload condition, in series with MOSFET Rds, load resistance of 3 ohm is present. Maximum of Input voltage drops across the load resistance part (3ohm) than across Rds=4.8milliohm. So vds drop will be very less (not Vds is close to Vin right?) & maximum current (18.33A limited by Rsense) can be allowed without crossing Power limit threshold.  If i am wrong, then how for 28V/9A (under full load condition= 9A) startsup successfully & works fine  ?

What is the type of load? Is it 28V/9A = 3.111 Ohm ?

Resistive load (3 ohm)

We can expect some variation in restart time from device to device as the fault detection and sink currents has tolerance. Is it matching if you consider 51uA, 1.25uA values. ?

Considering fault detection & sink current tolerance, for chosen 2.2uF timing capacitor;
Typical Restart time : 19.85 Seconds
Minimum Restart time : 13.259 seconds
Maximum restart time : 39.55 seconds
Under Overload & short circuit condition, observed restart time is not within the tolerance limit.

when 31.5V input applied, observed restart time is 14 seconds
Under overload fault condition, observed restart time is 80ms
Under short circuit condition, observed restart time is 1.8Seconds

Kindly clarify the above points.

Hi,

When Vin is applied and Vout=0V, the FET Vds= Vin

What is the type of load? Is it 28V/9A = 3.111 Ohm ? Resistive load (3 ohm)

Please share test waveform of Vin, Vout, GATE, input current.

Please schedule a call along with your TI-sales to discuss.

BR, Rakesh

Hi Balaji,

Shall we discuss over call ?

BR, Rakesh