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Test Module Pin Usage for TPS65920

Howard Robson
Intellectual 415 points
Other Parts Discussed in Thread: TPS65920

I am trying to finalize hookup of the test module pins in my design with the TPS65920.  The documentation has very little information on these pins:

TEST.RESET; TESTV1; TESTV2; TEST; JTAG.TDI/BERDATA and JTAG.TCK/BERCLK

The EVM has TEST and TEST.RESET open (no connection) and the rest tied to ground.

Any help would be appreciated, thank you.

  • 0
    TI__Genius 15100 points

    It is good practice to follow the documentation for the schematics. In this case the TEST and TEST.RESET are open may be because these have an internal pull-down, 100K and 50K respectively.

  • 0
    Prodigy 60 points

    Hi,

    TEST.RESET : This pin is used only for the simulation purpose to reduce the powerup sequence time by bypassing the debounce time. A transition of  HIGH to LOW and again LOW to HIGH  is needed.  This pin already has a internal pull down and hence can be left floating at the top.

    TESTV1/2 : These pins are used in test mode to observe the analog module outputs.To observe the voltage we have to do the analog test muxing (ATM) with which we can select the internal check point which we have to observe at the chip boundary.  With this, we can check voltage levels of modules like LDOs, DCDCs, References etc ..

    Regards,

    Kartik