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BQ76200: can't turn on DSG output of bq76200

Sebastian de Leon
Prodigy 190 points
Part Number: BQ76200

Hi all,

I’m having issues with the bq76200 in my hardware. My minimal setup is:

Pins DSG and CHG are left open, not driving any MOSFET, to make debug easier.

PACK+ is 25VDC, and voltage reaches pin 11 fine

BATT+ is 36VDC, and voltage reaches pin 2 fine.

RC filters to BAT and PACK pins are as specified by datasheet, using X7R 50V ceramic caps.

CP_EN is 3V, and CP cap has a voltage of 10.3VDC when CHG_EN and DSG_EN are 0.

CP Cap is 2.2uF 35V ceramic, very close to pins 1 and 2.

With CHG_EN and DCHG_EN both in 0, CHG pin copies BAT, and DCHG pin copies PACK.

My first concern up to this point is, why would I have a CP voltage of only 10.3V (almost in the UV limit of 9V), and not something more similar to 12 or 14VDC?

For the test, PMON_EN and PCHG_EN are driven low.

When I drive high CHG_EN (with 3V), leaving DCHG_EN low, CHG pin goes almost to BAT + Cap CP voltage, and voltage across CP cap stays in 10.3V. I guess this is fine, as it’s more than enough to turn on my unconnected MOSFETs.

When I drive high DCHG_EN (with 3V, leaving CHG_EN low), voltage across CP cap drops to 9.5V, and the pin DSG goes to only 28VDC, 3V over PACK pin.

When I drive both pins CHG_EN and DCHG_EN high, CHG pin stays in BAT voltage and DCHG pin goes to PACK voltage + 1.5V, and CP cap voltage is at 9.5V

For my understanding of the datasheet, I’m having under-voltage detection reading over the CP cap voltage in the bq76200 when driving high DSG_EN pin, but i’m not sure. Even if this is happening, I don’t understand why, as the CP cap value is fine (pins are not driving anything), and it’s well positioned in the layout.

I changed the bq76200 just in case it was faulty, but the problem persists. I still read the 2.2uF across the cap, so the cap is not damaged.

Please, any help will be much appreciated.

Thanks very much,

Sebastian

  • 0
    TI__Guru* 80963 points

    Hi Sebastian,

    The charge pump voltage is between 9V and 14V according to the datasheet - 10.3V is a common value.

    I think the issue is that the test conditions are a little different than what will happen during application conditions. When DSG goes high, it will try to drive to the charge pump voltage. However, this pin will not be able to drive the 21V above PACK+ (46V - 25V) - this will cause the ESD protection to turn on which will pull down the charge pump voltage. In the application, when the DSG FET turns on, it will cause the voltage on PACK+ to rise as well which will allow the DSG pin voltage to reach the charge pump voltage.

    If you change your test setup to raise the voltage on PACK+ to a higher value, you should see different results.

    Best regards,

    Matt