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Original question:

TPS3820: Phenomenon for Reset pin

TPS3824: How sensitive is TPS3824 to WDI transitions while asserting nRESET?

1138
Expert 1226 points
Part Number: TPS3824
Other Parts Discussed in Thread: TPS3123, TPS3852, TPS3125, TPS3124, TPS3126, TPS3851, TPS3850

The TPS3824 PMIC includes a watchdog capability which will assert its nRESET signal if its WDI input has not been toggled recently.  (In addition to asserting nRESET if the voltage supply being monitored is too low.)

This capability also includes a feature wherein if the WDI input is toggled while the TPS3824 is currently asserting nRESET then the TPS3824 enters a state wherein nRESET is latched, that is it is continuously asserted until the power to the TPS3824 is cycled, regardless of the state of any further watchdog servicing using WDI.

This feature represents a risk to our product.  If nRESET is latched, our product cannot function!  I appreciate that this risk can be ameliorated by using a FET to decouple WDI while nRESET is asserted; furthermore that replacing our TPS3824 with a TPS3823A could remove this risk entirely.  We are considering these options.  Right now, however, I would like to make sure we have this risk well characterized, in order to have a good understanding of our exposure.

How sensitive is the WDI logic while nRESET is asserted?  I assume that it cannot be as simple as "any H->L or L->H transitions on the WDI inputs while nRESET is asserted will cause nRESET to latch."  After all, the act of asserting nRESET itself has a reasonable chance of _causing_ a transition on the WDI input, given the range of circuitry the TPS3824 might be connected to.  Indeed, even if we use a FET to gate our WDI input, the act of switching WDI from being actively-driven to being high-impedance could conceivably be interpreted by the TPS3824 as a WDI transition.

As such, I have to believe that there's a bit of complexity there.  Perhaps the TPS3824 needs to see more than one WDI transition before it latches.  Perhaps it includes a time delay, where any WDI transitions that happen "soon" after nRESET is asserted are ignored.  Perhaps there is some other kind of filtering involved.

Can you please provide more detail as to how this latching feature works?  This would be of tremendous help in characterizing our risk.

--thx

  • 0
    TI__Genius 12630 points

    You understanding of TPS3824 functionality is correct.

    To address your concern for WDI sensitivity, the /RESET output has no impact at all on the WDI input and there is no chance for a /RESET activation or deactivation to cause a logic high or logic low signal transition on WDI. The input of WDI is a logic input defined by VIL and VIH in Table 7.3 of the datasheet and only a transition from one logic state to another will cause the latch. The act of switching WDI from being actively-driven to being high impedance will not be considered as a WDI transition as the device detects the high impedance state and will either generate its own pulse if not in reset condition or will do nothing until the watchdog is reinitialized once reset condition occurs.

    Is it possible to adjust your WDI signal such that the signal remains high or low until the reset is inactive?

  • 0
    TI__Genius 12630 points

    Hello,

    Just checking in to see if this item still needs support. Please feel free to email me directly at michaeldesando@ti.com for additional support. Thank you.

  • 0 in reply to Michael_DeSando
    Expert 1226 points

    Hello Michael,

    Thank you for following up!

    I appreciated your reply earlier, but it is possible that I wasn't clear earlier when I referred to nRESET having a plausible impact upon WDI.  I did not mean to suggest that there might be some connection internal between the TPS3824's nRESET and WDI lines.  I meant that it would not be unusual for a customer's circuitry attached to the TPS3824 to have some kind of dependency there.

    To look at it generally, the whole point of attaching the TPS3824's nRESET output to a circuit would be in order for that connection to be able to drive some kind of change in that circuit.  (Whatever that circuit might happen to be.)  In fact, it would be a common design for the nRESET input to the circuit to make a _significant_ change in the entirety of that circuit, including the possibility of placing all of that circuit's output to some kind of pre-determined state.

    Combined with that, a typical use case of the TPS3824's WDI input (at least, usually it's an input, I appreciate that the TPS3824's functioning is more complicated than that) would be to attach it to some part of the same circuit to which nRESET is also attached to.

    (For example, the nRESET output of the TPS3824 might connect directly to the nRESET of a microcontroller, and the WDI input of the TPS3824 might connect directly to a digital output of the same microcontroller.)

    As such, I expect that it is reasonably common for an assertion of nRESET by the TPS3824 to result in an impact on it's WDI input.  (For example, if a microcontroller happens to be driving WDI high, while nRESET is asserted, the hardware of the microcontroller (regardless of the firmware code) might switch, and then hold, WDI low.)

    In such a case, the risk is probably not that WDI would get toggled during the "middle" of time that nRESET was asserted.  WDI would only see a transition right around when nRESET transitioned.  Within nanoseconds or perhaps microseconds, most likely.

    You could call it a fast "glitch", if you wish.

    I appreciate that the data sheet describes gating the WDI line via a FET in order to break such a dependency between nRESET and WDI.

    However, I can image many designers thinking "I don't need to isolate the WDI line; there's no way we'd be toggling WDI while nRESET is active, our microcontroller / FPGA / discrete logic / what-have-you is in _RESET_ while nRESET is active!"  And not realizing that they are vulnerable to a "glitch" right when nRESET asserts.

    I can also imagine that even if a design includes a decoupling FET, that there might still be a potential for a "glitch", given the realities around real world components and potentially fast transition times and such.  Indeed, imagine a "race condition", if you were, where WDI happened to be starting a transition right at the same instant when the TPS3824 decided it had timed and and was about to assert nRESET.

    Well, at any rate, the details matter.  It had occurred to me that the design of the TPS3824 might be somewhat resilient to such "glitches".  For example, it might be deliberately ignore any transitions on WDI if they happen within, say, 5 microseconds of nRESET asserting.  Or, even if not officially designed for that purpose, it might happen to be reliably the case that the data sheet's "tw pulse width" (whatever that's trying to capture) of 100 nanoseconds has some kind of impact upon WDI sensitivity.

    In terms of our own situation, that's all a bit hypothetical.  It happens to be that our own circuitry driving WDI is completely separate from our circuitry connected to nRESET.  However, any information we have about how this aspect of the TPS3824 actually works in this regard will be helpful for our risk evaluation.

    What can you tell us about the TPS3824's sensitivity to WDI at the time of when it asserts nRESET?

    --thx

  • 0 in reply to 1138
    TI__Genius 12630 points

    The nRESET assertion time requires 25 us for a reset caused by voltage at VDD. The WDI pin recognizes pulse with width greater than 100 ns. This should give you the timing required to estimate the sensitivity at the moment reset is asserting and a watchdog input signal comes in. When you describe a "glitch" on WDI, the WDI pin has built in glitch immunity to ignore short transients less than 100 ns. When a pulse comes in on WDI while the device is in reset, this suggests that the device providing the WDI signal (MCU for example) has not correctly reset and hasn't correctly stopped sending WDI pulses to the WDI pin. This is the reason for latching the output. When reset is asserted, the MCU should detect the reset condition and then be able to stop the WDI pulse within the 1.6 second time window. The other options are to use TPS3823A or to use the decoupling FET as you previously mentioned. We also have watchdog devices without the latching feature such as the low voltage family (TPS3123, TPS3124, TPS3125, TPS3126, TPS2128) and the highly programmable family TPS3850, TPS3851, TPS3852. There are many ways to use these devices and I understand your concern with the latching functionality for TPS3824. I would recommend checking your specific configuration and seeing if it's possible to stop the WDI signal during a reset condition before the next WDI pulse is planned to arrive. If this is unknown, I recommend either adding the decoupling FET, or even a tri-state buffer will work, or switching to another device.

    We do not characterize the sensitivity of RESET assertion to WDI pulse arrival so there is no data that exists on this specific measurement. Typically a WDI rising or falling edge would be scheduled once per watchdog timeout period for example to prevent a watchdog timeout at 1.6 seconds. Once a reset occurs, there should still be enough time turn off the WDI pulse. For example a typical interrupt service routine might look like: RESET detected -> set WDI GPIO or PWM to high impedance -> service the undervoltage condition or timer fault -> wait until reset is released -> enable GPIO or PWM. Please let me know if you have any questions or need any further support.