TPS65185: TPS65185 from sleep state to wakeup state,

Hi,

Based on the power-up and power-down timing diagram in Figure 2 of the datasheet, the delay for PWR_GOOD coming out of the SLEEP state can be adjusted with UDLY1, UDLY2, UDLY3, and UDLY4. By default each of these delays is 6 ms, but they can each be reduced to 3 ms by writing 0 to register 0x0Ah. Would this be sufficient for your application?

I will need some additional information to determine if this is normal behavior:

1. What signal are you referencing this 65 ms power good delay? Is this the delay from WAKEUP to PWR_GOOD when WAKEUP is pulled high?

1. PWRUP is kept high.
2. WAKEUP is pulled low.
3. All rails are discharged, after which the device enters SLEEP state.
4. WAKEUP is then pulled high.

• Please provide scope shots of the following rails to verify the DDLYx, UDLYx, and power-down/power-up timings. Please show the rails during power-down (WAKEUP pulled low) and power-up (WAKEUP pulled back high). 

1. WAKEUP
2. VN
3. VB
4. VNEG
5. VEE
6. VPOS
7. VDDH
8. PWR_GOOD

Note from Figure 2 that, in addition to DDLYx, there is another 100 ms delay before VN discharges and the device can enter the SLEEP state. 

Thanks,

Gerard