LMR33620-Q1: About solder of SW terminal

Hi Koji,

To reduce dv/dt switching noise, the copper area on SW and BOOT node is normally arranged as small as possible. For LMR336X0 in VQFN package, trace connected to all other pins should be as larger as possible for better heat sinking, pls follow up the layout example on Fig52 for good EMI and thermal design.

Hi Andy-san

Thank you for quick response.

I report the layout pattern to my customer.

How about is the amount of SW soldering ?

Do you have the required value or recommended value ?

Best Regards,

Koji Hayashi

Hi Andy-san

Thank you for response.

SW pin (12 pin) is 87.7% recommended, but does it mean that you need to apply it completely considering the heat?

Best Regards,

Koji Hayashi.

Hi Koji,

It means that for Pin12, you need to place or print solder paste on its PCB pad by covering area of 87.7%, after SMT reflow process, the whole PCB pad area will be well soldered to package Pin12 pad,  too more paste area may cause solder bridge and less paste area will cause poor solder junction and heat sinking

Hi Andy-san

Thank you for quick response.

I understand the amount of SW soldering.

Is the following idea about heat dissipation correct ?

>・Heat is dissipated not only from this terminal but also from GND/VIN.
>・Since the SW pin pattern on the bottom side of the case cannot be arranged widely due to the structure of the package, heat dissipation can only be >expected to go to the outside of the case, so the dependence of the pattern under the case is low.

Best Regards,

Koji Hayashi

Hi Andy-san

I appreciate your swift response.

I understand.

Best Regards,

Koji Hayashi

Hi Andy-san

My customer have question.

There are differences depending on the package and manufacturer, but it is 30-50%.

On the other hand, 87.7% is a very large value. why ?

Do you have comparison results based on the amount of solder ?

Via is not placed in the pattern under the SW pad.

Does the heat spread even in that state ?

Best Regards,

Koji Hayashi

Hi Koji,

The solder pasted area 87.7% is based on 0.125 mm THICK STENCIL, it maybe lower percentage if use thicker stencil.

we just provide stencil design example for customer reference, customer can optimize it according their SMT process rule.

For better EMI performance, normally it's not recommended to place via on SW solder pad, PCB is the main heat sinking material to spread heat of Pin12 to bottom layer.

Hi Andy-san

Thank you for response.

I understand it is based on a 0.125mm thick stencil.

Why is the recommended 87.7% for SW pad only ?

Is it EMI ?

What is the impact if it is less than 87.7% ?

I understand that the heat from the SW pad is dissipated from the PCB.

Best Regards,

Koji Hayashi

Hi Koji,

Typically, the stencil apertures are reduced such that the solder paste coverage is 50% to 70% of the exposed pad area. For LMR336XX in QFN package, SW pin is the most hot pin as it located in package center and has biggest current flow than all other pins, so we recommended little higher coverage rate than 70% for better thermal performance, Not for EMI concern. 

Hi Andy-san

Thank you fro response.

I think that a large current flows not only to the SW but also to VIN and PGND.

Why only SW ?

87.8% is the solder paste printing area.

(datasheet P.46)

Is it correct ?

What is the recommended value for the solder joint area ?

Can you provide data on the relationship between ψJB and solder joint area ?

Best Regards,

Koji Hayashi

Hi Koji,

I think that a large current flows not only to the SW but also to VIN and PGND.

Why only SW ?----------SW pin average current=Iout, VIN pin current=Iout*duty cycle,  PGND current=Iout*(1--duty cycle)

87.8% is the solder paste printing area.

(datasheet P.46)

Is it correct ?---------Yes!

What is the recommended value for the solder joint area ?------------solder joint area should achieve 100% of pad size if solder paste printing area >70%

Can you provide data on the relationship between ψJB and solder joint area ?----------Sorry we don't such data and it's hard to do such kind of simulation

Hi Andy-san

Thank you for quick response.

>Why only SW ?----------SW pin average current=Iout, VIN pin current=Iout*duty cycle,  PGND current=Iout*(1--duty cycle)

I understand.

>87.8% is the solder paste printing area.

>(datasheet P.46)

>Is it correct ?---------Yes!

I understand.

>What is the recommended value for the solder joint area ?------------solder joint area should achieve 100% of pad size if solder paste printing area >70%

This IC recommended 87.8%,so 100% ?

>Can you provide data on the relationship between ψJB and solder joint area ?----------Sorry we don't such data and it's hard to do such kind of simulation

Do you have evaluation data ?

My customer wants to know how 87.8% was calculated.

When aiming at 87.8%, they think that it will cause solder balls.

Best Regards,

Koji Hayashi

Hi Andy-san

It is addition.

Do you have formulas or results that show the relationship between thermal information and solder joint area ? 

For example, RθJA or RθJC

Best Regards,
Koji Hayashi

Hi Koji,

The stencil aperture area is 2x0.812x0.25, the pad size is 1.825x0.25. so the coverage rate is about 87.7% if area loss of 4 aperture round corner also counted.

Pls end me email at andy.chen@ti.com, I will send you a calculator tool to estimate thermal resistance VS pad size. 

Hi Andy-san

Thank you for response.

I will send you email latter.

Best Regards,

Koji Hayashi