TPS7A7001: Selection of output ceramic capacitor

Hello Joe,

I would be happy to help. 

Equivalent models of capacitors - especially non ceramic capacitors - are complex.  Equivalent models for capacitors can be found on the manufacturer websites, and typically involve some form of ladder network to model the impedance correctly.  Even X7R ceramic capacitors are now being modeled as a ladder network on some manufacturer websites, although a simple series ESR - ESL - C model can be a good approximation.  The TI datasheet gives a good first estimate at whether your design will be stable, and this guidance is sufficient to evaluate the stability of most designs.  For those designs which involve more complex loads, I recommend the customer build a model of their loads - using manufacturer capacitor models - to evaluate how close they are to meeting the stability criteria.  Let me explain. 

It is important to note that the recommendations are for stability.  So the frequency of concern is where the internal loop gain crosses zero, or the internal bandwidth of the component.  There are many factors which affect the bandwidth, so a range of frequencies are involved.  We can start by saying that very low frequencies are not an issue, and very high frequencies are not a concern, because the bandwidth of the part is somewhere in the middle.

For the TPS7A7001, the datasheet specifies 4.7uF to 47uF capacitance without a feedforward capacitor, and 47uF to 200uF capacitance with a feedforward capacitor, as the range of stability.  As shown in figure 1 and 2, the ESR for most loads can range from 1m ohm (ceramic or polymer type capacitors) to 1 ohm (electrolytic capacitors) and in between (tantalum capacitors).  This load includes the setpoint resistors, so that may help your customer as no load is truly "0 amps". 

Once you have this information you can plot the equivalent impedance of the complex load across frequency, and check that it does not go outside of the range of stability.  An example simulation is provided below of a different LDO but using the same concept.  The upper impedance is dictated by the green line and the lower impedance is the red line.  The blue line is the impedance of a parallel combination of an electrolytic and ceramic capacitor, using manufacturer capacitor models.  At the high end the blue line goes above the green line, but since this is extremely high frequency - well above the bandwidth of the part - I know this part is stable with this load.  In this way your customer can evaluate their complex load against the TI datasheet.

Thanks,

- Stephen

Hi Joe,

For reference, here is the impedance curves with the TPS7A7001 limits and two capacitors.
The first plot shows an 0805, 10V, X7R, ceramic 10uF capacitor using a manufacturer online tool model.
The second plot shows an 0805, X5R, ceramic 10uF capacitor impedance across frequency from the manufacturer online tool.
A model did not exist of an X5R but this plot is still valuable for review.

The first plot is stable because the blue line is within the limits, within the bandwidth of the LDO.

The second plot is stable by visual inspection with the limits of the first plot.
So the EVM should be stable, at least at room temperature, which is where this data was simulated at.

Thanks,

- Stephen

Hi Joe,

That's exactly what I did.
If I were the customer I would gather models for my loads and repeat this exercise.
I would include tolerance across temperature and any other factors the customer would deem appropriate.

Any modern SPICE simulator can do this analysis in less than 1 second after the models are built.

Thanks,

- Stephen