This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Attached text file will be useful for the TPS65950/30/20 user to program the warm reset sequence and control the one or more resource with singular and broadcast messaging.
Kalirajan,
Searching for "TPS65950/30/20 filetype:txt" in google led me to the following document, hopefully it is the text file in question.
Best Regards,
Rick S.
[[
*********** TPS65950/30/20 advance warm reset programming example ***********
WARMRESET : The device can be configured to perform a warm reset of the system to bring system in known defined state by using the nRESWARM pin.
The minimum duration on the nRESWARM pin should be two 32KHz clock cycle.
A warm reset sequence programmed in device spare memory spaces by MEMORY_DATA and MEMORY_ADDRESS registers.
The starting address of this sequence need to program in SEQ_ADD_WARM register.
WARMRESET SEQUENCE CONFIGURATION STEPS
Step1: Program the warmreset sequence in spare memory word
<1> Configure the 16 bit WORD_MSG to control resource in OFF, ACTIVE and WARMRESET state
<2> Configure DELAY
<3> Configure the Next Address to control another resource or End Od Sequence address
Step2: Example of TI's WARMRESET SEQUENCE
Step3: Configure the starting address of the warmreset seq which is stored in spare memory
Step4: Enable warmreset sequence
Step5: Execute the warmreset sequence
############################################################
Step1: Program the warmreset sequence in spare memory word
############################################################
Sequence memory Structure as below, 0 to 42 memory address are hard coded with powr on and off sequence.
43 to 62 words are spare words in which user can program the Warmreset sequence or Sleep sequence.
63 word is to indicate the End of Sequence memory.
Sequence memory is composed of 64 words(64*4).
------------------------------------------------------------------
MEM |WORD_MSG_M |WORD_MSG_L | WORD_DELAY | WORD_JUMP |
ADDR |LSB_ADDR_00 |LSB_ADDR_01 |LSB_ADDR_10 |LSB_ADDR_11 |
------------------------------------------------------------------
0 | | | | |
1 | | | | |
3 | READ_ONLY | READ_ONLY | READ_ONLY | READ_WRITE |
4 | MEMORY | MEMORY | MEMORY | MEMORY |
. | | | | |
. | | | | |
-----------------------------------------------------------------
43 | | | | |
44 | SPARE | SPARE | SPARE | SPARE |
. | MEMORY | MEMORY | MEMORY | MEMORY |
. | WORD FOR | WORD FOR | WORD FOR | WORD FOR |
62 | WARMRESET | WARMRESET | WARMRESET | WARMRESET |
------------------------------------------------------------------
63 |END OF SEQ | | | |
------------------------------------------------------------------
There are tow 8 bit registers associated with the memory configuration i.e. MEMORY_ADDRESS and MEMORY_DATA.
If you write to data to spare address address then address will be incremented automatically.
In each word of sequence memory 4 bytes are stored so the address will be multiplied by 4.
So to write data to 45 memory word address will be 45*4.
Each memory word is divided into 4 bytes as like below :
[MEM_WORD] ==> PMB_MESSAGE BROADCAST or SINGULAR[31 downto 16], DELAY DIVIDER/TIMER[15 downto 8], NEXT_ADDRESS[7 downto 0]
####<1> Configure the 16 bit WORD_MSG to control resource in OFF, ACTIVE and WARMRESET state####
In the memory word [31:16] bits are allocated for the Power management message, this message may be Broadcast or Singular.
In Broadcast message one or more resources are controlled using the RES_GRP and RES_TYP
By using Singular message individual resource is controlled with its unique RES_ID.
Bits description for MEM_WORD[31:16] :
BROADCAST MESSAGE TYPE FORMAT, MT[28] = 1
-----------------------------------------------------------------------------------------------
|DEV_GRP[31:29] | MT[28] |RES_GRP[27:25] |RES_TYP2[24:23]RES_TYPE[22:20] | RES_STATE[19:16] |
-----------------------------------------------------------------------------------------------
SINGULAR MESSAGE TYPE FORMAT, MT[28] = 0
---------------------------------------------------------------
|DEV_GRP[31:29] | MT[28] |RES_ID [27:20] | RES_STATE[19:16] |
--------------------------------------------------------------
State Encodings: OFF = 0b0000, ACTIVE = 0b1110, WARMRESET = 0b1111, SLEEP = 0b1000
Example :
Singular message to Configure VDD1 in WARMRESET state its RES_IS is 15
SINGULAR MESSAGE IS
------------------------------
MEM_WORD[31:16] = | 111 | 0 |00001111 | 1111 |
------------------------------
Broadcast message to Configure Power Provider VDAC, VAUX1, VAUX3 and VMMC1 in OFF state
To control these resources together need to configure the same RES_TYPE2 field say 3 in all these PP registers and
broadcast the message using the RES_TYPE2 and RES_GRP fields.
--Configure the RES_TYPE2 to 3 in VDAC, VAUX1, VAUX3 and VMMC1
tlv_write_reg_i2c1("PM_RECEIVER_LDO_MMC_0_VMMC1_TYPE", 0x18)
tlv_write_reg_i2c1("PM_RECEIVER_LDO_MMC_0_VAUX1_TYPE", 0x18)
tlv_write_reg_i2c1("PM_RECEIVER_LDO_MMC_0_VAUX3_TYPE", 0x18)
tlv_write_reg_i2c1("PM_RECEIVER_LDO_MMC_0_VDAC_TYPE" , 0x18)
BROADCAST MESSAGE IS
-------------------------------
MEM_WORD[31:16] = | 111 | 1 |001 | 11000 |0000|
-------------------------------
####<2> Configure DELAY#####
DELAY DIVIDER/TIMER[15 downto 8] ==>
-------------------------------------------------------
|RSVD[15:14] |DIVIDER[13:12] | RSVD[11] | TIMER[10:8] |
-------------------------------------------------------
To calculate the delay we have to use the below table, the delay will be in 32k clock cycles.
------------------------------------------------------------------
DELAY | TIMER
-----------------------------------------------------------------
DIVIDER| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
-----------------------------------------------------------------
0 | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
-----------------------------------------------------------------
1 | 8 | 10 | 12 | 14 | 16 | 18 | 20 | 22 |
-----------------------------------------------------------------
2 | 24 | 28 | 32 | 36 | 40 | 44 | 48 | 52 |
-----------------------------------------------------------------
3 | 56 | 64 | 72 | 80 | 88 | 96 | 104 | 112 |
-----------------------------------------------------------------
Example : If the Delay is 14 then as per the above table DIVIDER = 1 and TIMER = 3,
Program this value in memory word[15:8] in divider and timer bits considering the reserved bits
-------------------
MEM_WORD[15 downto 8] = |00 |01 | 0 | 011 |
-------------------
####<3> Configure the Next Address to control another resource or End Od Sequence address####
NEXT_ADDRESS[7 downto 0] ==>
-----------------
|NEXT_ADDR[7:0] |
-----------------
Example : Next address to jump is EOS address i.e 63
-----------
MEM_WORD[7 downto 0] = |00111111 |
-----------
############################################################
Step2: Example of TI's WARMRESET SEQUENCE
############################################################
-----------------------------------------------------------------------------------------------
Steps RES_ID RES_GRP RES_Type2 Device_Resources Resource_State Delay(in 32-kHz clock)
0 27 X 0 Triton reset OFF 2
1 X All 1 Enable CLKEN, VINTANA1, ACTIVE 14
VINTDIG, and VINTANA2
2 X PP 2 Enable PP VAUX2, VAUX4, WARMRESET 14
VPLL2 and VMMC2
3 9 X 0 Enable PP VSIM WARMRESET 14
4 X PP 3 Disable PP VDAC, VMMC1 OFF 14
VAUX1 and VAUX3
5 15 X 0 Enable PP VDD1 WARMRESET 14
6 16 X 0 Enable PP VDD2 WARMRESET 14
7 7 X 0 Enable PP VPLL1 WARMRESET 96
8 25 X 0 Enable HFCLKOUT ACTIVE 2
9 27 X 0 Released Triton reset ACTIVE 2
----------------------------------------------------------------------------------------------
]]
--Configure the RES_TYPE2 to 1 in CLKEN, VINTDIG, VINTANA1 and VINTANA2
tlv_write_reg_i2c1("PM_RECEIVER_SIG_0_CLKEN_TYPE", 8)
tlv_write_reg_i2c1("PM_RECEIVER_LDO_INT_0_VINTDIG_TYPE", 8)
tlv_write_reg_i2c1("PM_RECEIVER_LDO_INT_0_VINTANA1_TYPE", 8)
tlv_write_reg_i2c1("PM_RECEIVER_LDO_INT_0_VINTANA2_TYPE" ,8)
--Configure the RES_TYPE2 to 2 in VPLL2, VAUX2, VAUX4 and VMMC2
tlv_write_reg_i2c1("PM_RECEIVER_LDO_MMC_0_VMMC2_TYPE", 16)
tlv_write_reg_i2c1("PM_RECEIVER_LDO_AUX_0_VAUX2_TYPE", 16)
tlv_write_reg_i2c1("PM_RECEIVER_LDO_AUX_0_VAUX4_TYPE", 16)
tlv_write_reg_i2c1("PM_RECEIVER_LDO_PLL_0_VPLL2_TYPE", 16)
--Configure the RES_TYPE2 to 3 in VDAC, VAUX1, VAUX3 and VMMC1
tlv_write_reg_i2c1("PM_RECEIVER_LDO_MMC_0_VMMC1_TYPE", 24)
tlv_write_reg_i2c1("PM_RECEIVER_LDO_AUX_0_VAUX1_TYPE", 24)
tlv_write_reg_i2c1("PM_RECEIVER_LDO_AUX_0_VAUX3_TYPE", 24)
tlv_write_reg_i2c1("PM_RECEIVER_LDO_DAC_0_VDAC_TYPE" , 24)
-- STEP 0: Singular Message to control the TRITON_RESET to OFF state
tlv_write_reg_i2c1("PM_MASTER_Memory_0_MEMORY_ADDRESS", 45*4) --ACTIVATE TRITON_RESET
tlv_write_reg_i2c1("PM_MASTER_Memory_0_MEMORY_DATA", 1) -WORD_MSG_M
tlv_write_reg_i2c1("PM_MASTER_Memory_0_MEMORY_DATA", 176) --WORD_MSG_L {MSG_M+MSG_L : 0b0000_00011011_0000 }
tlv_write_reg_i2c1("PM_MASTER_Memory_0_MEMORY_DATA", 2) --DELAY = 2 : Divider = 0 and Timer = 2
tlv_write_reg_i2c1("PM_MASTER_Memory_0_MEMORY_DATA", 46) --JUMP to 46
--STEP 1: Broadcast message to enable CLKEN, VINTDIG, VINTANA1 and VINTANA2
tlv_write_reg_i2c1("PM_MASTER_Memory_0_MEMORY_ADDRESS", 46*4)
tlv_write_reg_i2c1("PM_MASTER_Memory_0_MEMORY_DATA", 30) --WORD_MSG_M
tlv_write_reg_i2c1("PM_MASTER_Memory_0_MEMORY_DATA", 142) --WORD_MSG_L {MSG_M+MSG_L : 0b000_1_111_01000_1110 }
tlv_write_reg_i2c1("PM_MASTER_Memory_0_MEMORY_DATA", 19) --DELAY = 14 : Divider = 1 and Timer = 3
tlv_write_reg_i2c1("PM_MASTER_Memory_0_MEMORY_DATA", 47) --JUMP to 47
-- STEP 2: Broadcast message to enable VPLL2, VAUX2, VAUX4 and VMMC2
tlv_write_reg_i2c1("PM_MASTER_Memory_0_MEMORY_ADDRESS", 47*4)
tlv_write_reg_i2c1("PM_MASTER_Memory_0_MEMORY_DATA", 19) --WORD_MSG_M
tlv_write_reg_i2c1("PM_MASTER_Memory_0_MEMORY_DATA", 15) --WORD_MSG_L {MSG_M+MSG_L : 0b000_1_001_10000_1111 }
tlv_write_reg_i2c1("PM_MASTER_Memory_0_MEMORY_DATA", 19) --DELAY = 14 : Divider = 1 and Timer = 3
tlv_write_reg_i2c1("PM_MASTER_Memory_0_MEMORY_DATA", 48) --JUMP to 48
-- STEP 3: Singular message to control VSIM warmreset
tlv_write_reg_i2c1("PM_MASTER_Memory_0_MEMORY_ADDRESS", 48*4)
tlv_write_reg_i2c1("PM_MASTER_Memory_0_MEMORY_DATA", 0) --WORD_MSG_M
tlv_write_reg_i2c1("PM_MASTER_Memory_0_MEMORY_DATA", 159) --WORD_MSG_L {MSG_M+MSG_L : 0b0000_00001001_1111 }
tlv_write_reg_i2c1("PM_MASTER_Memory_0_MEMORY_DATA", 19) --DELAY = 14 : Divider = 1 and Timer = 3
tlv_write_reg_i2c1("PM_MASTER_Memory_0_MEMORY_DATA", 49) --JUMP to 49
-- STEP 4: Broadcast message to disable VDAC, VAUX1, VAUX3 and VMMC1
tlv_write_reg_i2c1("PM_MASTER_Memory_0_MEMORY_ADDRESS", 49*4)
tlv_write_reg_i2c1("PM_MASTER_Memory_0_MEMORY_DATA", 19) --WORD_MSG_M
tlv_write_reg_i2c1("PM_MASTER_Memory_0_MEMORY_DATA", 128) --WORD_MSG_L {MSG_M+MSG_L : 0b000_1_001_11000_0000 }
tlv_write_reg_i2c1("PM_MASTER_Memory_0_MEMORY_DATA", 19) --DELAY = 14 : Divider = 1 and Timer = 3
tlv_write_reg_i2c1("PM_MASTER_Memory_0_MEMORY_DATA", 50) --JUMP to 49
-- singular message to VDD1 to set in WARMRESET
tlv_write_reg_i2c1("PM_MASTER_Memory_0_MEMORY_ADDRESS", 50*4) --VDD1 WARMRESET
tlv_write_reg_i2c1("PM_MASTER_Memory_0_MEMORY_DATA", 0) --WORD_MSG_M
tlv_write_reg_i2c1("PM_MASTER_Memory_0_MEMORY_DATA", 255) --WORD_MSG_L {MSG_M+MSG_L : 0b0000_00001111_1111 }
tlv_write_reg_i2c1("PM_MASTER_Memory_0_MEMORY_DATA", 19) --DELAY = 14 : Divider = 1 and Timer = 3
tlv_write_reg_i2c1("PM_MASTER_Memory_0_MEMORY_DATA", 51) --JUMP to 50
-- singular message to VDD2 to set in WARMRESET
tlv_write_reg_i2c1("PM_MASTER_Memory_0_MEMORY_ADDRESS", 51*4) --VDD2 WARMRESET
tlv_write_reg_i2c1("PM_MASTER_Memory_0_MEMORY_DATA", 1) --WORD_MSG_M
tlv_write_reg_i2c1("PM_MASTER_Memory_0_MEMORY_DATA", 15) --WORD_MSG_L {MSG_M+MSG_L : 0b0000_00010000_1111 }
tlv_write_reg_i2c1("PM_MASTER_Memory_0_MEMORY_DATA", 19) --DELAY = 14 : Divider = 1 and Timer = 3
tlv_write_reg_i2c1("PM_MASTER_Memory_0_MEMORY_DATA", 52) --JUMP to 51
-- singular message to VPLL1 to set in WARMRESET
tlv_write_reg_i2c1("PM_MASTER_Memory_0_MEMORY_ADDRESS", 52*4) --VPLL1 WARMRESET
tlv_write_reg_i2c1("PM_MASTER_Memory_0_MEMORY_DATA", 0) --WORD_MSG_M
tlv_write_reg_i2c1("PM_MASTER_Memory_0_MEMORY_DATA", 127) --WORD_MSG_L {MSG_M+MSG_L : 0b0000_00000111_1111 }
tlv_write_reg_i2c1("PM_MASTER_Memory_0_MEMORY_DATA", 53) --DELAY = 96: Divider = 3 and Timer = 5
tlv_write_reg_i2c1("PM_MASTER_Memory_0_MEMORY_DATA", 53) --JUMP to 52
-- singular message to HFCLKOUT to set in WARMRESET
tlv_write_reg_i2c1("PM_MASTER_Memory_0_MEMORY_ADDRESS", 53*4) --HFCLKOUT WARMRESET
tlv_write_reg_i2c1("PM_MASTER_Memory_0_MEMORY_DATA", 1) --WORD_MSG_M
tlv_write_reg_i2c1("PM_MASTER_Memory_0_MEMORY_DATA", 63) --WORD_MSG_L {MSG_M+MSG_L : 0b0000_00010011_1111 }
tlv_write_reg_i2c1("PM_MASTER_Memory_0_MEMORY_DATA", 2) --DELAY = 2: Divider = 0 and Timer = 2
tlv_write_reg_i2c1("PM_MASTER_Memory_0_MEMORY_DATA", 54) --JUMP to 53
--Singular Message to control the TRITON_RESET to ACTIVE state
tlv_write_reg_i2c1("PM_MASTER_Memory_0_MEMORY_ADDRESS", 54*4) --DEACTIVATE TRITON_RESET
tlv_write_reg_i2c1("PM_MASTER_Memory_0_MEMORY_DATA", 1) --WORD_MSG_M
tlv_write_reg_i2c1("PM_MASTER_Memory_0_MEMORY_DATA", 190) --WORD_MSG_L {MSG_M+MSG_L : 0b0000_00011011_1110 }
tlv_write_reg_i2c1("PM_MASTER_Memory_0_MEMORY_DATA", 2) --DELAY = 2 : Divider = 0 and Timer = 2
tlv_write_reg_i2c1("PM_MASTER_Memory_0_MEMORY_DATA", 63) --JUMP to END OF SEQUENCE
--###########################################################################################
-- Step3: Configure the starting address of the warmreset seq which is stored in spare memory
--############################################################################################
--Configure the starting address of the warmreset seq which is stored in spare memory (here 45 address location) in SEQ_ADD_WARM register.
tlv_write_reg_i2c1("PM_MASTER_Memory_0_SEQ_ADD_WARM", 45)
--############################################################
-- Step4: Enable warmreset sequence
--############################################################
WRITE_STATIC(nRESWARM, 1)
--Enable WARMRESET feature for all processors
tlv_write_reg_i2c1("PM_MASTER_Events_0_P1_SW_EVENTS", 16*1)
tlv_write_reg_i2c1("PM_MASTER_Events_0_P2_SW_EVENTS", 16*1)
tlv_write_reg_i2c1("PM_MASTER_Events_0_P3_SW_EVENTS", 16*1)
--############################################################
-- Step5: Execute the warmreset sequence
--############################################################
WRITE_STATIC(nRESWARM, 0)
-- wait delay oftwo 32k cycles and release nRESWARM pin to high
WRITE_STATIC(nNRESWARM, 1)