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TPS65381A-Q1: How to use the Registers.

Kengo.Y
Guru 11165 points
Part Number: TPS65381A-Q1

Hi team.

Could you tell me my questions?

1. Can I read ''SAFETY_CHECK_CTRL Register'' when the status is Diagnostic?

2. In ''Device Status Flag Byte Response'' , I'd like to read and write.

    How to set the STAT[3],[2],[1] ?

Sincerely.

Kengo. 

  • 0
    TI__Genius 17380 points

    Hello Kengo,

    Our device expert is currently on business travel so there may be some delay in response. In the meantime I can ask for some clarification:

    I don't see anything that suggests SAFETY_CHECK_CTRL register would be inaccessible in Diagnostic state, is there a specific concern?

    I don't understand the second question. The STAT bits are sent from the PMIC back to the MCU to let it review the previous communication results if that is part of the MCU functionality. If you want to control whether you read / write with the current command it is done with the CMD bits outlined in Figure 5-17.

    https://sps16.itg.ti.com/sites/BMC/IPM/_layouts/15/start.aspx#/Lists/DeviceInfo/AllItems.aspx

  • 0 in reply to Kevin LaRosa
    TI__Mastermind 20590 points

    Hello Kengo,

    For your first question, Kevin is correct.  SAFETY_CHECK_CTRL and all registers can be read in DIAGNOSTIC state.  All registers can be read in any the powered states including DIAGNOSTIC, ACTIVE and SAFE state.

    Only writing to some registers has the limitation of occurring only in DIAGNOSTIC state and some registers can be locked against writing with a software lock command. The write access limitations are highlighed in the register map of the datasheet if the specific register has a limitation against writing, an example is below. 

    As Kevin mentioned, the STAT bits are read only bits shifted out on the SDO pin while the command portion of the SPI frame is being shifted into the device.  This byte is intended to provide a short status overview back to the MCU and software on each SPI frame.  

  • 0 in reply to Scott Monroe
    Guru 11165 points

    Hi Kevin-san, Scott-san.

    Thank you so much your kindly replies.

    Let me know one more thing.

    Are there limitation for other register depending on the value of ''Device Status Flag'' ?

    Sincerely.

    Kengo.

  • 0 in reply to Kengo.Y
    TI__Mastermind 20590 points

    Hi Kengo,

    I assume you mean Device Status Flag Byte Response when you wrote "Device Status Flag".  This flag byte is simply a byte of information provided by the TPS65381A-Q1 with every SPI frame (output).  This byte does not have any impact on the register write restrictions.  Register write restrictions (for writable registers) that have restrictions are based on the device state and the lock/un-lock command as outlined register by register in the Write section of the register's Controller acces description.  One example of this is below from the DEV_CFG1 register:

    Controller access:

    Read (RD_DEV_CFG1)

    Write (WR_DEV_CFG1). Write update can only occur in the DIAGNOSTIC state. Write access locked through SW_LOCK command.



  • 0 in reply to Scott Monroe
    Guru 11165 points

    Hi Scott.

    I have one more question.

    Is it OK to read and write even if there is an spi error?

    Sincerely.

    Kengo.

  • 0 in reply to Kengo.Y
    TI__Mastermind 20590 points

    Hi Kengo,

    If your system is giving you SPI errors, it is indicating that there is a set up and timing issue with the SPI.  You can continue to try to read/write, but with a detected SPI error at the PMIC side during a write, the PMIC will not accept the write and the read may be invalid at the MCU side.  

    Please check the hardware connections, parasitic loading on the SPI and SPI settings in the MCU to get solid SPI communication and avoid SPI errors.  On any SPI error the read or write should be repeated since the SPI frame with the error was incorrect.

  • 0 in reply to Scott Monroe
    Guru 11165 points

    Hi Scott.

    I have one more question again...

    How long is the time for SPI writing?

    My customer used %MHz for clock.

    Timing for communication is 2ms.

    Sincerely.

    Kengo.

  • 0 in reply to Kengo.Y
    TI__Mastermind 20590 points

    Hi Kengo,

    I cannot answer your question since you do not have the full information on the timing you are using in the MCU for your SPI settings.  The SPI frame timing is very simple, please refer to section 5.5.1.5 SPI Frame Overview in the datasheet to see what a SPI frame should look like from the MCU.  The actual frame will be as long as NCS is low plus two device internal clock cycles (2 x 250 ns +/- 5%) once NCS returns high to transfer a write into the internal logic.  The SPI frame timing from the MCU must follow the SPI timing requirements from Electrical Characteristics table 4.6 Timing Requirements.

     

  • 0 in reply to Scott Monroe
    Guru 11165 points

    Hi Scott.

    Thank you for your reply.

    My customer said ,

    when it is read in the next cycle after writing, the reply is ''writing is in progress''.

    So, please tell me how long I should wait after writing.

    If you need any information you need to answer , please let me know.

    Sincerely.

    Kengo.

  • 0 in reply to Kengo.Y
    TI__Mastermind 20590 points

    Hi Kengo,

    There is no bit or indicator of a "writing in progress" on this PMIC.  Is the customer mis-interpreting the STAT[3] bit explained in section 5.5.1.3 Device Status Flag Byte Response that indicates the last SPI frame was a write?  What is the state of STAT[0] bit?  STAT[0] indicates SPI error in previous frame. 

    The SPI timing requirements as I explained previously are in the datasheet, section Electrical Characteristics table 4.6 Timing Requirements.  As can be seen in this section the hold time where NCS has to be high after a SPI write is parameter thlcs, with 788 ns minimum hold time of NCS (high) after a SPI frame.