LM5170-Q1: Duty cycle when ISETA=0V

Toshihiro Watanabe

Part Number: LM5170-Q1
Other Parts Discussed in Thread: LM5170

Hello,

We set ISETA=GND and expected duty cycle is 0% and no switching but we can see the short glitch pulse on LO pin for driving MOSFET.

I guess duty cycle isn't 0% but it becomes very small duty cycle. Is this thinkable operation of LM5170?

Best regards,

Toshihiro Watanabe

over 5 years ago

0 Richard Fu22 over 5 years ago

TI__Mastermind 31065 points

Hi Watanabe-san,

The engineer responsible for this part is currently out of office. He will be back by the week of the 28th.

Thanks,

Richard

0 Toshihiro Watanabe over 5 years ago in reply to Richard Fu22

TI__Genius 10235 points

Hello,

The week of the 28th is in two week. Could someone support this?

Best regards,

Toshihiro Watanabe

0 Youhao Xi over 5 years ago in reply to Toshihiro Watanabe

TI__Guru* 78110 points

Hi Watanabe-san,

Like just mentioned in the reply to your another post, I am currently on a biz trip and my reply can be delayed.

What mode do you refer to, the buck mode or the boost mode? If it is the boost mode, what you see is caused by the internal offset voltage (a few mV) at the gm amplifier. The solution is to add a charge pump circuit as showing below, which can help overcome the gm offset voltage and achieve no load regulation in the boost mode.

Boost No Load Regulation Solution.pdf

Thanks,

Youhao

0 Toshihiro Watanabe over 5 years ago in reply to Youhao Xi

TI__Genius 10235 points

Hello Youhao-san,

I think charge pump is negative bias circuit. When SW1 or SW2 node is switches, negative bias rail will be around -1.3V which sets ISEA voltage below 0V. This can cancel gm offset voltage. Is my understanding correct?

Best regards,

Toshihiro Watanabe

0 Youhao Xi over 5 years ago in reply to Toshihiro Watanabe

TI__Guru* 78110 points

Hi Watanabe-san,

Yes, you are right about it.

Best Regards,

Youhao Xi

Power management

Power management forum

LM5170-Q1: Duty cycle when ISETA=0V