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TPS65721: 2.25 MHz buck followed by an LDO

Nick Alexeev
Intellectual 605 points
Part Number: TPS65721
Other Parts Discussed in Thread: TPS717

Folks,

I’m reading the datasheet for the TPS65721 (linear charger with buck converter and LDO). Fig. 23 shows a typical application towards a Bluetooth power supply. The TPS65721 generates the +1.85V supply rail for Bluetooth in two stages: buck, then LDO.

The buck is witching at 2.25 MHz. Does the LDO have an appreciable PSRR at 2.25 MHz? Power supply rejection of a good LDO (like TPS717) is only up to about 1 MHz.

my question: What’s the merit of following a high frequency buck with an LDO?

Any suggestion, insight or reference is really appreciated!

Cheers,

- Nick

  • 0
    TI__Mastermind 30280 points

    LDOs always clean up power supplies. They never introduce noise.

    The Buck is not always switching at 2.25 MHz. See the Power Save Mode section on page 25 of the TPS65721 datasheet. The default operation is that power save mode, or PFM, is allowed. As a result, the buck is allowed to skip pules as needed, so the buck could be switching at an effective frequency of 1.125MHz, 563kHz, etc.

  • 0 in reply to Brian Berner
    Intellectual 605 points

    Let's say that I'd like a to have a power supply rail with low ripple (and I'd like to do it with a buck-then-LDO approach) for Bluetooth and a few sensors.  400 mA. 
    What would produce a cleaner supply rail?  What would produce a better solution in general?

    1. A buck switching at a moderate frequency (say 500 kHz).  Output capacitors with good enough ESR (but not exceptionally low ESR).  LDO with high PSRR.

    2. Or, a buck switching at a high frequency (say 2 MHz).  Output capacitor with extra low ESR.  (Additional stage of filtering?)  No LDO.

    Do we have an application note about buck-then-LDO and the surrounding trade-offs, by any chance?

  • 0 in reply to Nick Alexeev
    TI__Mastermind 30280 points

    Nick,

    I do not think there is any data specific to the TPS65721 that is available, but power for CMOS Image Sensors typically uses a cascaded Buck-->LDO topology.

    You can review the test data from these designs to see the effect of an LDO (spec'd at 1MHz for PSRR) after a Buck switching at >2MHz.

    TIDA-01130 (discrete regulators)

    TIDUD97 (PMIC)

    Let me know if you are able to draw a conclusion based on this test data.