TPS65950 Issues

What is your VBAT level? The VBAT needs to be > 3.2V for the device to power up correctly.

If the VBAT level is correct then I suspect that your layout has problems on the VDD1 input. You are probably seeing in-rush current problems. Please monitor your VBAT on the scope when you see the REGEN and other rail going low. I would expect that VBAT is dropping for a short time. This would happen if the input traces on VDD1 (or other switchers) are not thick enough to handle the current. If you confirm this as your problem then you can see if these traces are on the top layer. If you can add a capacitor on this path to hold the rail from dropping then it may be a workaround you can try. Alternatively if you have a way to add a blue wire (assuming the trace is tiny for a short length) then this may also work.

A permanent fix would be to rectify this on next board spin. See also - http://community.ti.com/forums/t/2897.aspx 

Let me know if this is your problem, if not we can debug further.

Gandhar,

I believe you are correct.  I do see some inrush noise at the VDD1.IN pin.  I have set my VBAT at 3.6V nominal.  With the noise, looks like it

might be dropping below the magical 3.2V.  Have tried tieing heaver wires in, added caps etc but to no avail.  I am considering increasing

VBAT to 4.2V nominal and see it I can keep it going.  Does this sound reasonable?

Thanks.

You can go upto VBAT=4.5V. I doubt if that will help though.

Gandar,

Looks like I need to re-layout the VDD1 input lans.  Any idea what the inrush current I can expect on this part?  Anyother large currents I should

know about?

Thanks.

Loren

PS  I tried driving VBAT up, and find that if you exceed 4.0VDC you latch the part up (goes into a high current mode).  The data sheet says I can

go to 4.5VDC.

You can refer to this - http://community.ti.com/forums/t/3692.aspx for details on layout.

Also look at this site for Layout guidelines - http://focus.ti.com/docs/prod/folders/print/tps65950.html

I guess your DCDC traces were probably thinner than 6mils.

I did not get the latch up part. I have powered this device on my board with 4.5V without any problems. Please explain more on this. Are you sure this is not because of the thin traces.

Gandhar,

Thanks for hanging with me on this design.  We are going back for another spin.  My traces will be at least 6mil on this next go round.  It appears that the VDD1

is the problematic supply in terms of inrush current.  I'm thinking I'll be alright one I get bigger lans.  Anything else I should know about before I send the

board out?

Loren

If you follow the layout guidelines then you will not have any problems.

Gandhar,

One thing I noticed with the TPS65950 (and my current layout) the part will run fine for a period of time, and then go into a high current mode.  What can

cause the part to go to this high current mode?  Am I loosing a clock, burning the part up, what.  Once it get into this (latched-up) mode, it's time for a new

part.

I have never seen such an issue. It is bad. Losing a clock will not have such an effect.

How long does the device work fine? I am asking to see how much time do you have to debug this problem. If you power down the device when you see the current rising, does the device power-up again properly?

Can you isolate the other connections on the TPS65950 and see if you see the same behavior. This would give some more informaton. Also, it may be the layout causing this problem, you fixed your first problem and now something else came up.

Could the TEST pins be a problem (cause the chip to go high current)?  I am following the app note connection guidelines, but the boards from Mistral have a

different pin configuration for the TEST pins.

TEST pins will not have such a drastic effect. If you are following the app note guidelines then you are doing the right thing.

Loren -

Did you ever discover a root cause for your high current mode (latch-up) condition?    We have recently seen some parts with the same condition you describe and have not been able to identify a root cause. 

Mike